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Dataflow Mirroring: Architectural Support for Highly Efficient Fine-Grained Spatial Multitasking on Systolic-Array NPUs

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dc.contributor.authorLee, Jounghoo-
dc.contributor.authorChoi, Jinwoo-
dc.contributor.authorKim, Jaeyeon-
dc.contributor.authorLee, Jinho-
dc.contributor.authorKim, Youngsok-
dc.date.accessioned2024-05-02T05:42:40Z-
dc.date.available2024-05-02T05:42:40Z-
dc.date.created2024-04-23-
dc.date.created2024-04-23-
dc.date.issued2021-
dc.identifier.citation2021 58TH ACM/IEEE DESIGN AUTOMATION CONFERENCE (DAC), pp.247-252-
dc.identifier.issn0738-100X-
dc.identifier.urihttps://hdl.handle.net/10371/200475-
dc.description.abstractWe present dataflow mirroring, architectural support for low-overhead fine-grained systolic array allocation which overcomes the limitations of prior coarse-grained spatial-multitasking Neural Processing Unit (NPU) architectures. The key idea of dataflow mirroring is to reverse the dataflows of co-located Neural Networks (NNs) in horizontal and/or vertical directions, allowing allocation boundaries to be set between any adjacent rows and columns of a systolic array and supporting up to four-way spatial multitasking. Our detailed experiments using MLPerf NNs and a dataflow-mirroring-augmented NPU prototype which extends Google's TPU with dataflow mirroring shows that dataflow mirroring can significantly improve the multitasking performance by up to 46.4%.-
dc.language영어-
dc.publisherIEEE-
dc.titleDataflow Mirroring: Architectural Support for Highly Efficient Fine-Grained Spatial Multitasking on Systolic-Array NPUs-
dc.typeArticle-
dc.identifier.doi10.1109/DAC18074.2021.9586312-
dc.citation.journaltitle2021 58TH ACM/IEEE DESIGN AUTOMATION CONFERENCE (DAC)-
dc.identifier.wosid000766079700042-
dc.identifier.scopusid2-s2.0-85109948613-
dc.citation.endpage252-
dc.citation.startpage247-
dc.description.isOpenAccessN-
dc.contributor.affiliatedAuthorLee, Jinho-
dc.type.docTypeProceedings Paper-
dc.description.journalClass1-
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  • College of Engineering
  • Department of Electrical and Computer Engineering
Research Area AI Accelerators, Distributed Deep Learning, Neural Architecture Search

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