A Diagnosable Network-on-Chip for FPGA Verification of Intellectual Properties

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A Diagnosable Network-on-Chip for FPGA Verification of Intellectual Properties

DC Field	Value	Language
dc.contributor.author	Han, Kyuseung	-
dc.contributor.author	Lee, Jae-Jin	-
dc.contributor.author	Lee, Woojoo	-
dc.contributor.author	Lee, Jinho	-
dc.date.accessioned	2024-05-02T06:01:08Z	-
dc.date.available	2024-05-02T06:01:08Z	-
dc.date.created	2024-04-23	-
dc.date.created	2024-04-23	-
dc.date.created	2024-04-23	-
dc.date.issued	2019-03	-
dc.identifier.citation	IEEE Design and Test, Vol.36 No.2, pp.81-87	-
dc.identifier.issn	2168-2356	-
dc.identifier.uri	https://hdl.handle.net/10371/200534	-
dc.description.abstract	Editor's note: Debug and validation are important steps required to ensure that systems-on-chip satisfies the design specs. This article presents an elegant diagnosis technique integrated within the network-on-chip infrastructure. The authors demonstrate the proposed technique on an FPGA prototype.-Umit Y. Ogras, Arizona State University	-
dc.language	한국어	-
dc.publisher	IEEE Computer Society	-
dc.title	A Diagnosable Network-on-Chip for FPGA Verification of Intellectual Properties	-
dc.type	Article	-
dc.identifier.doi	10.1109/MDAT.2018.2890238	-
dc.citation.journaltitle	IEEE Design and Test	-
dc.identifier.wosid	000464913400007	-
dc.identifier.scopusid	2-s2.0-85059419870	-
dc.citation.endpage	87	-
dc.citation.number	2	-
dc.citation.startpage	81	-
dc.citation.volume	36	-
dc.description.isOpenAccess	N	-
dc.contributor.affiliatedAuthor	Lee, Jinho	-
dc.type.docType	Article	-
dc.description.journalClass	1	-
dc.subject.keywordAuthor	debugging	-
dc.subject.keywordAuthor	FPGA verification	-
dc.subject.keywordAuthor	Network-on-chip	-