Publications

Detailed Information

Tree-mesh heterogeneous topology for low-latency NoC

DC Field Value Language
dc.contributor.authorHan, Sungju-
dc.contributor.authorLee, Jinho-
dc.contributor.authorChoi, Kiyoung-
dc.date.accessioned2024-05-02T06:07:12Z-
dc.date.available2024-05-02T06:07:12Z-
dc.date.created2024-04-11-
dc.date.created2024-04-11-
dc.date.issued2014-12-
dc.identifier.citationACM International Conference Proceeding Series, Vol.23-26-September-2014, pp.19-24-
dc.identifier.issn0000-0000-
dc.identifier.urihttps://hdl.handle.net/10371/200658-
dc.description.abstractIn Network-on-Chip (NoC), topology is one of the most important design choices that determine performance and power consumption. Mesh, being the most popular NoC topology for many researches and products, is mainly tailored towards high throughput. However, many researches show that NoCs rarely operate under heavy load and that latency is often much more critical in practice. In this paper, we show that by adding a small tree network to assist the baseline mesh network, the zero-load latency can be greatly reduced while still maintaining the high throughput. For the management of the hybrid network, we propose a novel algorithm to steer each packet to different networks based on hop-count gain and contention monitoring. Experimental results show improvement on not only synthetic traffic but also real application workloads. Copyright 2014 ACM.-
dc.language영어-
dc.publisherAssociation for Computing Machinery-
dc.titleTree-mesh heterogeneous topology for low-latency NoC-
dc.typeArticle-
dc.identifier.doi10.1145/2685342.2685346-
dc.citation.journaltitleACM International Conference Proceeding Series-
dc.identifier.scopusid2-s2.0-84984674330-
dc.citation.endpage24-
dc.citation.startpage19-
dc.citation.volume23-26-September-2014-
dc.description.isOpenAccessY-
dc.contributor.affiliatedAuthorLee, Jinho-
dc.contributor.affiliatedAuthorChoi, Kiyoung-
dc.type.docTypeConference Paper-
dc.description.journalClass1-
dc.subject.keywordAuthorHeterogeneity-
dc.subject.keywordAuthorNetwork-on-chip-
dc.subject.keywordAuthorTopology-
Appears in Collections:
Files in This Item:
There are no files associated with this item.

Related Researcher

  • College of Engineering
  • Department of Electrical and Computer Engineering
Research Area AI Accelerators, Distributed Deep Learning, Neural Architecture Search

Altmetrics

Item View & Download Count

  • mendeley

Items in S-Space are protected by copyright, with all rights reserved, unless otherwise indicated.

Share