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A Charge Recycling Logic Data Links for Single-and Multiple-Channel I/Os

DC Field Value Language
dc.contributor.authorWu, Han-
dc.contributor.authorPark, Jeong Hoan-
dc.contributor.authorJiang, Rucheng-
dc.contributor.authorChoi, Jung-Hwan-
dc.contributor.authorYoo, Jerald-
dc.date.accessioned2024-05-03T04:30:13Z-
dc.date.available2024-05-03T04:30:13Z-
dc.date.created2024-05-02-
dc.date.issued2023-10-
dc.identifier.citationIEEE Journal of Solid-State Circuits, Vol.58 No.10, pp.2790-2800-
dc.identifier.issn0018-9200-
dc.identifier.urihttps://hdl.handle.net/10371/200772-
dc.description.abstractWide input-output (IO) chip-to-chip interfaces, such as 3-D chip stacking through-silicon via (TSV), silicon interposer in high-bandwidth memory (HBM), and other 2.5-D chip-to-chip interface, handle a large amount of data in the server and artificial intelligence (AI) applications. With a large number of IOs, power consumption becomes a huge burden. This article presents a novel charge recycling (CR) logic with >20% power reduction under random data streaming. The presented generic CR technique is applicable to both TSV and transmission line (T-Line) link IOs. The CR logic is implemented on two silicon dies where the single-channel CR (CR1) uses a storage capacitor to recycle charge at each data transition and multi-channel CR (CR2/4/8) replenishes the charge between multiple channels during the opposite transitions. Fabricated in a 40-nm 1P8M standard CMOS, the TSV link (2.56 Gb/s) and the T-Line link (5.12 Gb/s) save energy up to 32.2% and 47%, respectively, under periodic data transmission and up to >20% under pseudo-random binary sequence (PRBS). The eye diagrams and the bit error rate (BER) show that signal integrity is maintained when compared with conventional data links.-
dc.language영어-
dc.publisherInstitute of Electrical and Electronics Engineers-
dc.titleA Charge Recycling Logic Data Links for Single-and Multiple-Channel I/Os-
dc.typeArticle-
dc.identifier.doi10.1109/JSSC.2023.3294475-
dc.citation.journaltitleIEEE Journal of Solid-State Circuits-
dc.identifier.wosid001051256200001-
dc.identifier.scopusid2-s2.0-85168285772-
dc.citation.endpage2800-
dc.citation.number10-
dc.citation.startpage2790-
dc.citation.volume58-
dc.description.isOpenAccessY-
dc.contributor.affiliatedAuthorYoo, Jerald-
dc.type.docTypeArticle-
dc.description.journalClass1-
dc.subject.keywordAuthorRandom access memory-
dc.subject.keywordAuthorThrough-silicon vias-
dc.subject.keywordAuthorClocks-
dc.subject.keywordAuthorRecycling-
dc.subject.keywordAuthorCapacitors-
dc.subject.keywordAuthorVoltage-
dc.subject.keywordAuthorResistance-
dc.subject.keywordAuthorCharge recycling (CR)-
dc.subject.keywordAuthordata links-
dc.subject.keywordAuthorenergy efficiency-
dc.subject.keywordAuthorenergy recycling-
dc.subject.keywordAuthorenergy reduction ratio (ERR)-
dc.subject.keywordAuthorhigh-bandwidth memory (HBM)-
dc.subject.keywordAuthorI/O-
dc.subject.keywordAuthorthrough-silicon via (TSV)-
dc.subject.keywordAuthortransmission line (T-Line)-
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Yoo, Jerald유담
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  • College of Engineering
  • Department of Electrical and Computer Engineering
Research Area Biomedical Applications, Energy-Efficient Integrated Circuits

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