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A Charge Recycling Logic Data Links for Single-and Multiple-Channel I/Os
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Wu, Han | - |
dc.contributor.author | Park, Jeong Hoan | - |
dc.contributor.author | Jiang, Rucheng | - |
dc.contributor.author | Choi, Jung-Hwan | - |
dc.contributor.author | Yoo, Jerald | - |
dc.date.accessioned | 2024-05-03T04:30:13Z | - |
dc.date.available | 2024-05-03T04:30:13Z | - |
dc.date.created | 2024-05-02 | - |
dc.date.issued | 2023-10 | - |
dc.identifier.citation | IEEE Journal of Solid-State Circuits, Vol.58 No.10, pp.2790-2800 | - |
dc.identifier.issn | 0018-9200 | - |
dc.identifier.uri | https://hdl.handle.net/10371/200772 | - |
dc.description.abstract | Wide input-output (IO) chip-to-chip interfaces, such as 3-D chip stacking through-silicon via (TSV), silicon interposer in high-bandwidth memory (HBM), and other 2.5-D chip-to-chip interface, handle a large amount of data in the server and artificial intelligence (AI) applications. With a large number of IOs, power consumption becomes a huge burden. This article presents a novel charge recycling (CR) logic with >20% power reduction under random data streaming. The presented generic CR technique is applicable to both TSV and transmission line (T-Line) link IOs. The CR logic is implemented on two silicon dies where the single-channel CR (CR1) uses a storage capacitor to recycle charge at each data transition and multi-channel CR (CR2/4/8) replenishes the charge between multiple channels during the opposite transitions. Fabricated in a 40-nm 1P8M standard CMOS, the TSV link (2.56 Gb/s) and the T-Line link (5.12 Gb/s) save energy up to 32.2% and 47%, respectively, under periodic data transmission and up to >20% under pseudo-random binary sequence (PRBS). The eye diagrams and the bit error rate (BER) show that signal integrity is maintained when compared with conventional data links. | - |
dc.language | 영어 | - |
dc.publisher | Institute of Electrical and Electronics Engineers | - |
dc.title | A Charge Recycling Logic Data Links for Single-and Multiple-Channel I/Os | - |
dc.type | Article | - |
dc.identifier.doi | 10.1109/JSSC.2023.3294475 | - |
dc.citation.journaltitle | IEEE Journal of Solid-State Circuits | - |
dc.identifier.wosid | 001051256200001 | - |
dc.identifier.scopusid | 2-s2.0-85168285772 | - |
dc.citation.endpage | 2800 | - |
dc.citation.number | 10 | - |
dc.citation.startpage | 2790 | - |
dc.citation.volume | 58 | - |
dc.description.isOpenAccess | Y | - |
dc.contributor.affiliatedAuthor | Yoo, Jerald | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.subject.keywordAuthor | Random access memory | - |
dc.subject.keywordAuthor | Through-silicon vias | - |
dc.subject.keywordAuthor | Clocks | - |
dc.subject.keywordAuthor | Recycling | - |
dc.subject.keywordAuthor | Capacitors | - |
dc.subject.keywordAuthor | Voltage | - |
dc.subject.keywordAuthor | Resistance | - |
dc.subject.keywordAuthor | Charge recycling (CR) | - |
dc.subject.keywordAuthor | data links | - |
dc.subject.keywordAuthor | energy efficiency | - |
dc.subject.keywordAuthor | energy recycling | - |
dc.subject.keywordAuthor | energy reduction ratio (ERR) | - |
dc.subject.keywordAuthor | high-bandwidth memory (HBM) | - |
dc.subject.keywordAuthor | I/O | - |
dc.subject.keywordAuthor | through-silicon via (TSV) | - |
dc.subject.keywordAuthor | transmission line (T-Line) | - |
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- College of Engineering
- Department of Electrical and Computer Engineering
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