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Extending and Programming the NVMe I/O Determinism Interface for Flash Arrays

DC Field Value Language
dc.contributor.authorLi, Huaicheng-
dc.contributor.authorPutra, Martin L.-
dc.contributor.authorShi, Ronald-
dc.contributor.authorKurnia, Fadhil, I-
dc.contributor.authorLin, Xing-
dc.contributor.authorDo, Jae Young-
dc.contributor.authorKistijantoro, Achmad Imam-
dc.contributor.authorGanger, Gregory R.-
dc.contributor.authorGunawi, Haryadi S.-
dc.date.accessioned2024-05-09T06:42:09Z-
dc.date.available2024-05-09T06:42:09Z-
dc.date.created2024-05-09-
dc.date.issued2023-02-
dc.identifier.citationACM Transactions on Storage, Vol.19 No.1, p. 5-
dc.identifier.issn1553-3077-
dc.identifier.urihttps://hdl.handle.net/10371/201361-
dc.description.abstractPredictable latency on flash storage is a long-pursuit goal, yet unpredictability stays due to the unavoidable disturbance from many well-known SSD internal activities. To combat this issue, the recent NVMe IO Determinism (IOD) interface advocates host-level controls to SSD internalmanagement tasks. Although promising, challenges remain on how to exploit it for truly predictable performance. We present IODA,1 an I/O deterministic flash array design built on top of small but powerful extensions to the IOD interface for easy deployment. IODA exploits data redundancy in the context of IOD for a strong latency predictability contract. In IODA, SSDs are expected to quickly fail an I/O on purpose to allowpredictable I/Os through proactive data reconstruction. In the case of concurrent internal operations, IODA introduces busy remaining time exposure and predictable-latency-window formulation to guarantee predictable data reconstructions. Overall, IODA only adds five new fields to the NVMe interface and a small modification in the flash firmware while keeping most of the complexity in the host OS. Our evaluation shows that IODA improves the 95-99.99th latencies by up to 75x. IODA is also the nearest to the ideal, no disturbance case compared to seven state-of-the-art preemption, suspension, GC coordination, partitioning, tiny-tail flash controller, prediction, and proactive approaches.-
dc.language영어-
dc.publisherAssociation for Computing Machinary, Inc.-
dc.titleExtending and Programming the NVMe I/O Determinism Interface for Flash Arrays-
dc.typeArticle-
dc.identifier.doi10.1145/3568427-
dc.citation.journaltitleACM Transactions on Storage-
dc.identifier.wosid000939530200005-
dc.identifier.scopusid2-s2.0-85149441435-
dc.citation.number1-
dc.citation.startpage5-
dc.citation.volume19-
dc.description.isOpenAccessN-
dc.contributor.affiliatedAuthorDo, Jae Young-
dc.type.docTypeArticle-
dc.description.journalClass1-
dc.subject.keywordPlusMEMORY-
dc.subject.keywordAuthorSoftware/hardware co-design-
dc.subject.keywordAuthorpredictable latency-
dc.subject.keywordAuthorSSD-
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  • Department of Electrical and Computer Engineering
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