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Nonvolatile and Neuromorphic Memory Devices Using Interfacial Traps in Two-Dimensional WSe2/MoTe2 Stack Channel

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dc.contributor.authorPark, Sam-
dc.contributor.authorJeong, Yeonsu-
dc.contributor.authorJin, Hye-Jin-
dc.contributor.authorPark, Junkyu-
dc.contributor.authorJang, Hyenam-
dc.contributor.authorLee, Sol-
dc.contributor.authorHuh, Woong-
dc.contributor.authorCho, Hyunmin-
dc.contributor.authorShin, Hyung Gon-
dc.contributor.authorKim, Kwanpyo-
dc.contributor.authorLee, Chul-Ho-
dc.contributor.authorChoi, Shinhyun-
dc.contributor.authorIm, Seongil-
dc.date.accessioned2024-05-16T01:10:40Z-
dc.date.available2024-05-16T01:10:40Z-
dc.date.created2023-04-19-
dc.date.issued2020-09-
dc.identifier.citationACS Nano, Vol.14 No.9, pp.12064-12071-
dc.identifier.issn1936-0851-
dc.identifier.urihttps://hdl.handle.net/10371/202249-
dc.description.abstractVery recently, stacked two-dimensional materials have been studied, focusing on the van der Waals interaction at their stack junction interface. Here, we report field effect transistors (FETs) with stacked transition metal dichalcogenide (TMD) channels, where the heterojunction interface between two TMDs appears useful for nonvolatile or neuromorphic memory FETs. A few nanometer-thin WSe2 and MoTe2 flakes are vertically stacked on the gate dielectric, and bottom p-MoTe, performs as a channel for hole transport. Interestingly, the WSe2/MoTe2 stack interface functions as a hole trapping site where traps behave in a nonvolatile manner, although trapping/detrapping can be controlled by gate voltage (V-GS). Memory retention after high V-GS pulse appears longer than 10000 s, and the Program/Erase ratio in a drain current is higher than 200. Moreover, the traps are delicately controllable even with small V-GS, which indicates that a neuromorphic memory is also possible with our heterojunction stack FETs. Our stack channel FET demonstrates neuromorphic memory behavior of similar to 94% recognition accuracy.-
dc.language영어-
dc.publisherAmerican Chemical Society-
dc.titleNonvolatile and Neuromorphic Memory Devices Using Interfacial Traps in Two-Dimensional WSe2/MoTe2 Stack Channel-
dc.typeArticle-
dc.identifier.doi10.1021/acsnano.0c05393-
dc.citation.journaltitleACS Nano-
dc.identifier.wosid000615915300013-
dc.identifier.scopusid2-s2.0-85091561478-
dc.citation.endpage12071-
dc.citation.number9-
dc.citation.startpage12064-
dc.citation.volume14-
dc.description.isOpenAccessN-
dc.contributor.affiliatedAuthorLee, Chul-Ho-
dc.type.docTypeArticle-
dc.description.journalClass1-
dc.subject.keywordAuthorstack channel FET-
dc.subject.keywordAuthorWSe2/MoTe2 heterojunction-
dc.subject.keywordAuthorinterface traps-
dc.subject.keywordAuthornonvolatile memory-
dc.subject.keywordAuthorneuromorphic device-
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  • College of Engineering
  • Department of Electrical and Computer Engineering
Research Area 2차원 반도체 소자 및 재료, High-Performance 2D Electronics, Low-Power 2D Electronics, 뉴로모픽 소자 및 응용기술, 저전력 소자 및 소자물리

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