Publications

Detailed Information

A 48-Gb/s Single-Ended PAM-4 Receiver with Adaptive Nonlinearity Compensation

DC Field Value Language
dc.contributor.authorKim, Kahyun-
dc.contributor.authorYun, Daeho-
dc.contributor.authorBaek, Kyungmin-
dc.contributor.authorChoi, Woo-Seok-
dc.contributor.authorJeong, Deog-Kyoon-
dc.date.accessioned2024-05-16T01:21:28Z-
dc.date.available2024-05-16T01:21:28Z-
dc.date.created2023-09-15-
dc.date.created2023-09-15-
dc.date.created2023-09-15-
dc.date.issued2023-05-
dc.identifier.citationIEEE International Symposium on Circuits and Systems proceedings, Vol.2023-May, p. 190917-
dc.identifier.issn0271-4302-
dc.identifier.urihttps://hdl.handle.net/10371/202454-
dc.description.abstractThis paper presents a 48-Gb/s single-ended PAM4 receiver (RX) with an adaptive nonlinearity compensating equalizer. The receiver incorporates 3 parallel Cherry-Hooper continuous-time linear equalizers (CTLEs) and a 1-tap 9-coefficient adaptive decision feedback equalizer (DFE). CTLEs provide a variable gain with offset-canceling calibration. The DFE detects the level separation mismatch ratio (RLM) of the transmitted data and nonlinear distortion within the receiver analog front-end (AFE). The nonlinearity is compensated by simultaneously adapting 9 coefficients of the nonlinearity compensator. The proposed RX is fabricated in the 40nm CMOS technology, occupying 0.236 mm(2). Measured in a 7-dB loss channel, the RX achieves a BER of less than 10-12 and energy efficiency of 2.97 pJ/b.-
dc.language영어-
dc.publisherIEEE International Symposium on Circuits and Systems proceedings-
dc.titleA 48-Gb/s Single-Ended PAM-4 Receiver with Adaptive Nonlinearity Compensation-
dc.typeArticle-
dc.identifier.doi10.1109/ISCAS46773.2023.10182132-
dc.citation.journaltitleIEEE International Symposium on Circuits and Systems proceedings-
dc.identifier.wosid001038214602176-
dc.identifier.scopusid2-s2.0-85167720352-
dc.citation.startpage190917-
dc.citation.volume2023-May-
dc.description.isOpenAccessN-
dc.contributor.affiliatedAuthorChoi, Woo-Seok-
dc.contributor.affiliatedAuthorJeong, Deog-Kyoon-
dc.type.docTypeProceedings Paper-
dc.description.journalClass1-
dc.subject.keywordAuthorFour-level pulse amplitude modulation (PAM-4)-
dc.subject.keywordAuthorsingle-ended receiver (RX)-
dc.subject.keywordAuthoradaptive decision feedback equalizer (DFE)-
dc.subject.keywordAuthorCherry-Hooper continuous-time linear equalizer (CTLE)-
dc.subject.keywordAuthorlevel separation mismatch ratio (RLM)-
Appears in Collections:
Files in This Item:
There are no files associated with this item.

Related Researcher

  • College of Engineering
  • Department of Electrical and Computer Engineering
Research Area DRAM-PIM, High Bandwidth Memory Interface, O Links, Performance Modeling for I

Altmetrics

Item View & Download Count

  • mendeley

Items in S-Space are protected by copyright, with all rights reserved, unless otherwise indicated.

Share