A Highly Linear Digitally Controlled Delay Line with Reduced Duty Cycle Distortion

Abstract

Digitally controlled delay lines (DCDLs) have been implemented to provide variable delays and used for circuits like digital-to-time converters and timing recovery circuits. The conventional DCDLs using only either PMOSCAPs or NMOSCAPs are prone to duty cycle distortion, which often necessitates additional duty cycle correction circuits in many applications. In this paper, a highly linear DCDL with reduced duty cycle distortion is proposed and designed in a 28nm CMOS process. By incorporating both PMOSCAPs and NMOSCAPs, the amount of duty cycle distortion has been reduced to maximum of 5.7%, which is 7.7 times smaller than that of the conventional DCDL. Moreover, by keeping the amount of capacitance for each digital control word as linear as possible, the proposed DCDL achieves very good linearity with differential nonlinearity (DNL) smaller than 0.15LSB.