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A 12-Gb/s 10-ns Turn-On Time Rapid ON/OFF Baud-Rate DFE Receiver in 65-nm CMOS

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dc.contributor.authorKim, Dongwook-
dc.contributor.authorAhmed, Mostafa G.-
dc.contributor.authorChoi, Woo-Seok-
dc.contributor.authorElkholy, Ahmed-
dc.contributor.authorHanumolu, Pavan Kumar-
dc.date.accessioned2024-05-16T01:22:33Z-
dc.date.available2024-05-16T01:22:33Z-
dc.date.created2020-08-21-
dc.date.created2020-08-21-
dc.date.created2020-08-21-
dc.date.issued2020-08-
dc.identifier.citationIEEE Journal of Solid-State Circuits, Vol.55 No.8, pp.2196-2205-
dc.identifier.issn0018-9200-
dc.identifier.urihttps://hdl.handle.net/10371/202483-
dc.description.abstractRapid ON/OFF (ROO) operation helps scale power in accordance with link utilization. In this article, we present a baud-rate ROO receiver that can turn on in just 10 ns (similar to 120 UI). Baud-rate clock and data recovery (CDR) is implemented using a new timing function that is amenable to operation with a loop un-rolled decision feedback equalizer (DFE). The receiver is turned on rapidly by sweeping the recovered clock phase across the received data bit by offsetting the digitally controlled oscillator (DCO) frequency at each power-ON event. This first ROO DFE receiver also includes a continuous-time linear equalizer (CTLE) and three-tap DFE to compensate up to 20-dB channel loss at Nyquist. Fabricated in a 65-nm CMOS process, the prototype receiver recovers 12 Gb/s with BER < 10(-12) and achieves a >30-MHz JTOL corner, 377 f s(rms) recovered clock jitter, and 3.8-pJ/bit energy efficiency.-
dc.language영어-
dc.publisherInstitute of Electrical and Electronics Engineers-
dc.titleA 12-Gb/s 10-ns Turn-On Time Rapid ON/OFF Baud-Rate DFE Receiver in 65-nm CMOS-
dc.typeArticle-
dc.identifier.doi10.1109/JSSC.2020.2978138-
dc.citation.journaltitleIEEE Journal of Solid-State Circuits-
dc.identifier.wosid000552195700016-
dc.identifier.scopusid2-s2.0-85081624269-
dc.citation.endpage2205-
dc.citation.number8-
dc.citation.startpage2196-
dc.citation.volume55-
dc.description.isOpenAccessN-
dc.contributor.affiliatedAuthorChoi, Woo-Seok-
dc.type.docTypeArticle-
dc.description.journalClass1-
dc.subject.keywordPlusTRANSCEIVER-
dc.subject.keywordPlusRECOVERY-
dc.subject.keywordPlusCLOCK-
dc.subject.keywordPlusLINK-
dc.subject.keywordAuthorTiming-
dc.subject.keywordAuthorReceivers-
dc.subject.keywordAuthorClocks-
dc.subject.keywordAuthorDecision feedback equalizers-
dc.subject.keywordAuthorGain-
dc.subject.keywordAuthorInsertion loss-
dc.subject.keywordAuthorBaud rate-
dc.subject.keywordAuthorburst mode-
dc.subject.keywordAuthorclock and data recovery (CDR)-
dc.subject.keywordAuthordecision feedback equalizer (DFE)-
dc.subject.keywordAuthorrapid ON-
dc.subject.keywordAuthorOFF (ROO)-
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  • College of Engineering
  • Department of Electrical and Computer Engineering
Research Area DRAM-PIM, High Bandwidth Memory Interface, O Links, Performance Modeling for I

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