A 0.016 mm&lt;SUP&gt;2&lt;/SUP&gt; 0.26-μW/MHz 60-240-MHz Digital PLL With Delay-Modulating Clock Buffer in 65 nm CMOS

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A 0.016 mm<SUP>2</SUP> 0.26-μW/MHz 60-240-MHz Digital PLL With Delay-Modulating Clock Buffer in 65 nm CMOS

DC Field	Value	Language
dc.contributor.author	Zhu, Junheng	-
dc.contributor.author	Choi, Woo Seok	-
dc.contributor.author	Hanumolu, Pavan Kumar	-
dc.date.accessioned	2024-05-17T07:36:11Z	-
dc.date.available	2024-05-17T07:36:11Z	-
dc.date.created	2024-05-17	-
dc.date.issued	2019-08	-
dc.identifier.citation	IEEE Journal of Solid-State Circuits, Vol.54 No.8, pp.2186-2194	-
dc.identifier.issn	0018-9200	-
dc.identifier.uri	https://hdl.handle.net/10371/203144	-
dc.language	영어	-
dc.publisher	Institute of Electrical and Electronics Engineers	-
dc.title	A 0.016 mm2 0.26-μW/MHz 60-240-MHz Digital PLL With Delay-Modulating Clock Buffer in 65 nm CMOS	-
dc.type	Article	-
dc.identifier.doi	10.1109/JSSC.2019.2915021	-
dc.citation.journaltitle	IEEE Journal of Solid-State Circuits	-
dc.identifier.wosid	000477712900009	-
dc.identifier.scopusid	2-s2.0-85069872812	-
dc.citation.endpage	2194	-
dc.citation.number	8	-
dc.citation.startpage	2186	-
dc.citation.volume	54	-
dc.description.isOpenAccess	N	-
dc.contributor.affiliatedAuthor	Choi, Woo Seok	-
dc.description.journalClass	1	-