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A 15-Gb/s Sub-Baud-Rate Digital CDR
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Kim, Dongwook | - |
dc.contributor.author | Choi, Woo Seok | - |
dc.contributor.author | Elkholy, Ahmed | - |
dc.contributor.author | Kenney, Jack | - |
dc.contributor.author | Hanumolu, Pavan Kumar | - |
dc.date.accessioned | 2024-05-17T07:36:20Z | - |
dc.date.available | 2024-05-17T07:36:20Z | - |
dc.date.created | 2024-05-17 | - |
dc.date.issued | 2019-03 | - |
dc.identifier.citation | IEEE Journal of Solid-State Circuits, Vol.54 No.3, pp.685-695 | - |
dc.identifier.issn | 0018-9200 | - |
dc.identifier.uri | https://hdl.handle.net/10371/203147 | - |
dc.description.abstract | This paper presents a sub-baud-rate clock and data recovery (CDR) circuit that can recover clock and data using only differential quarter-rate clocks. A combination of eight samplers and an integrator recover four data bits in each clock cycle. Four of the eight samplers are re-used for phase detection as well as for background calibration to improve the robustness of the CDR to process, voltage, and temperature variations. A continuous-time linear equalizer is used to compensate for inter-symbol interference up to 11 dB. The CDR prototype fabricated in a 65-nm CMOS recovers 15.2-Gb/s data using only differential 3.8-GHz clock and achieves bit error rate (BER) < 10(-12), > 10-MHz jitter tolerance (JTOL) corner, and 548 fsrms recovered clock jitter. The total power consumption is 29 mW, which translates to an energy efficiency of 1.9 pJ/bit. | - |
dc.language | 영어 | - |
dc.publisher | Institute of Electrical and Electronics Engineers | - |
dc.title | A 15-Gb/s Sub-Baud-Rate Digital CDR | - |
dc.type | Article | - |
dc.identifier.doi | 10.1109/JSSC.2018.2885540 | - |
dc.citation.journaltitle | IEEE Journal of Solid-State Circuits | - |
dc.identifier.wosid | 000459692800008 | - |
dc.identifier.scopusid | 2-s2.0-85062440565 | - |
dc.citation.endpage | 695 | - |
dc.citation.number | 3 | - |
dc.citation.startpage | 685 | - |
dc.citation.volume | 54 | - |
dc.description.isOpenAccess | N | - |
dc.contributor.affiliatedAuthor | Choi, Woo Seok | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.subject.keywordPlus | DFE | - |
dc.subject.keywordPlus | RECOVERY | - |
dc.subject.keywordAuthor | Baud-rate | - |
dc.subject.keywordAuthor | clock and data recovery (CDR) | - |
dc.subject.keywordAuthor | current integrator | - |
dc.subject.keywordAuthor | digital CDR | - |
dc.subject.keywordAuthor | phase detector (PD) | - |
dc.subject.keywordAuthor | sub-baud-rate | - |
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- College of Engineering
- Department of Electrical and Computer Engineering
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