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A 15-Gb/s Sub-Baud-Rate Digital CDR

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dc.contributor.authorKim, Dongwook-
dc.contributor.authorChoi, Woo Seok-
dc.contributor.authorElkholy, Ahmed-
dc.contributor.authorKenney, Jack-
dc.contributor.authorHanumolu, Pavan Kumar-
dc.date.accessioned2024-05-17T07:36:20Z-
dc.date.available2024-05-17T07:36:20Z-
dc.date.created2024-05-17-
dc.date.issued2019-03-
dc.identifier.citationIEEE Journal of Solid-State Circuits, Vol.54 No.3, pp.685-695-
dc.identifier.issn0018-9200-
dc.identifier.urihttps://hdl.handle.net/10371/203147-
dc.description.abstractThis paper presents a sub-baud-rate clock and data recovery (CDR) circuit that can recover clock and data using only differential quarter-rate clocks. A combination of eight samplers and an integrator recover four data bits in each clock cycle. Four of the eight samplers are re-used for phase detection as well as for background calibration to improve the robustness of the CDR to process, voltage, and temperature variations. A continuous-time linear equalizer is used to compensate for inter-symbol interference up to 11 dB. The CDR prototype fabricated in a 65-nm CMOS recovers 15.2-Gb/s data using only differential 3.8-GHz clock and achieves bit error rate (BER) < 10(-12), > 10-MHz jitter tolerance (JTOL) corner, and 548 fsrms recovered clock jitter. The total power consumption is 29 mW, which translates to an energy efficiency of 1.9 pJ/bit.-
dc.language영어-
dc.publisherInstitute of Electrical and Electronics Engineers-
dc.titleA 15-Gb/s Sub-Baud-Rate Digital CDR-
dc.typeArticle-
dc.identifier.doi10.1109/JSSC.2018.2885540-
dc.citation.journaltitleIEEE Journal of Solid-State Circuits-
dc.identifier.wosid000459692800008-
dc.identifier.scopusid2-s2.0-85062440565-
dc.citation.endpage695-
dc.citation.number3-
dc.citation.startpage685-
dc.citation.volume54-
dc.description.isOpenAccessN-
dc.contributor.affiliatedAuthorChoi, Woo Seok-
dc.type.docTypeArticle-
dc.description.journalClass1-
dc.subject.keywordPlusDFE-
dc.subject.keywordPlusRECOVERY-
dc.subject.keywordAuthorBaud-rate-
dc.subject.keywordAuthorclock and data recovery (CDR)-
dc.subject.keywordAuthorcurrent integrator-
dc.subject.keywordAuthordigital CDR-
dc.subject.keywordAuthorphase detector (PD)-
dc.subject.keywordAuthorsub-baud-rate-
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  • College of Engineering
  • Department of Electrical and Computer Engineering
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