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A 0.45-0.7 V 1-6 Gb/s 0.29-0.58 pJ/b Source-Synchronous Transceiver Using Near-Threshold Operation
Cited 10 time in
Web of Science
Cited 13 time in Scopus
- Authors
- Issue Date
- 2018-03
- Citation
- IEEE Journal of Solid-State Circuits, Vol.53 No.3, pp.884-895
- Abstract
- A low-power source-synchronous multi-Gb/s transceiver is presented. Supply voltage is aggressively scaled to reduce power, and the speed penalty resulting from low-voltage operation is overcome by multiplexing transmitter/receiver synchronized by low-rate multi-phase clocks. Phase spacing errors incurred by device mismatches are corrected using a self-calibration scheme. The proposed phase calibration method uses a single digital DLL to calibrate all the phases, which makes it insensitive to offsets in the calibrating DLL. Fabricated in a 65-nm CMOS process, energy efficiency and data rate of the prototype transceiver vary from 0.29 to 0.58 pJ/bit and 1 to 6 Gb/s, respectively, as the supply voltage changes from 0.45 to 0.7 V.
- ISSN
- 0018-9200
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- There are no files associated with this item.
Related Researcher
- College of Engineering
- Department of Electrical and Computer Engineering
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