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A 5GHz Digital Fractional-N PLL Using a 1-bit Delta-Sigma Frequency-to-Digital Converter in 65 nm CMOS : A 5GHz Digital Fractional-<i>N</i> PLL Using a 1-bit Delta-Sigma Frequency-to-Digital Converter in 65 nm CMOS
DC Field | Value | Language |
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dc.contributor.author | Talegaonkar, Mrunmay | - |
dc.contributor.author | Anand, Tejasvi | - |
dc.contributor.author | Elkholy, Ahmed | - |
dc.contributor.author | Elshazly, Amr | - |
dc.contributor.author | Nandwana, Romesh Kumar | - |
dc.contributor.author | Saxena, Saurabh | - |
dc.contributor.author | Young, Brian | - |
dc.contributor.author | Choi, Woo Seok | - |
dc.contributor.author | Hanumolu, Pavan Kumar | - |
dc.date.accessioned | 2024-05-17T07:37:24Z | - |
dc.date.available | 2024-05-17T07:37:24Z | - |
dc.date.created | 2024-05-17 | - |
dc.date.issued | 2017-09 | - |
dc.identifier.citation | IEEE Journal of Solid-State Circuits, Vol.52 No.9, pp.2306-2320 | - |
dc.identifier.issn | 0018-9200 | - |
dc.identifier.uri | https://hdl.handle.net/10371/203167 | - |
dc.description.abstract | A highly digital two-stage fractional-N phaselocked loop (PLL) architecture utilizing a first-order 1-bit Delta Sigma frequency-to-digital converter (FDC) is proposed and implemented in a 65nm CMOS process. Performance of the first-order 1-bit Delta Sigma FDC is improved by using a phase interpolator-based fractional divider that reduces phase quantizer input span and by using a multiplying delay-locked loop that increases its oversampling ratio. We also describe an analogy between a time-to-digital converter (TDC) and a Delta Sigma FDC followed by an accumulator that allows us to leverage the TDC-based PLL analysis techniques to study the impact of Delta Sigma FDC characteristics on Delta Sigma FDC-based fractional-N PLL (FDCPLL) performance. Utilizing proposed techniques, a prototype PLL achieves 1 MHz bandwidth, -101.6 dBc/Hz in-band phase noise, and 1.22psrms (1 kHz-40 MHz) jitter while generating 5.031GHz output from 31.25MHz reference clock input. For the same output frequency, the stand-alone second-stage fractional-N FDCPLL achieves 1MHz bandwidth, -106.1dBc/Hz in-band phase noise, and 403 fsrms jitter with a 500MHz reference clock input. The two-stage PLL consumes 10.1mW power from a 1V supply, out of which 7.1 mW is consumed by the second-stage FDCPLL. | - |
dc.language | 영어 | - |
dc.publisher | Institute of Electrical and Electronics Engineers | - |
dc.title | A 5GHz Digital Fractional-N PLL Using a 1-bit Delta-Sigma Frequency-to-Digital Converter in 65 nm CMOS | - |
dc.title.alternative | A 5GHz Digital Fractional-N PLL Using a 1-bit Delta-Sigma Frequency-to-Digital Converter in 65 nm CMOS | - |
dc.type | Article | - |
dc.identifier.doi | 10.1109/JSSC.2017.2718670 | - |
dc.citation.journaltitle | IEEE Journal of Solid-State Circuits | - |
dc.identifier.wosid | 000408338600009 | - |
dc.identifier.scopusid | 2-s2.0-85028704894 | - |
dc.citation.endpage | 2320 | - |
dc.citation.number | 9 | - |
dc.citation.startpage | 2306 | - |
dc.citation.volume | 52 | - |
dc.description.isOpenAccess | Y | - |
dc.contributor.affiliatedAuthor | Choi, Woo Seok | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.subject.keywordPlus | LOCKED LOOP | - |
dc.subject.keywordPlus | SYNTHESIZER | - |
dc.subject.keywordPlus | MODULATOR | - |
dc.subject.keywordAuthor | Delta Sigma frequency-to-digital converter (FDC) | - |
dc.subject.keywordAuthor | digital PLL | - |
dc.subject.keywordAuthor | fractional divider | - |
dc.subject.keywordAuthor | fractional-N PLL | - |
dc.subject.keywordAuthor | multiplying delay-locked loop (MDLL) | - |
dc.subject.keywordAuthor | phase interpolator (PI) | - |
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- College of Engineering
- Department of Electrical and Computer Engineering
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