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A 2.8mW/Gb/s 14Gb/s Serial Link Transceiver in 65nm CMOS

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dc.contributor.authorSaxena, Saurabh-
dc.contributor.authorShu, Guanghua-
dc.contributor.authorNandwana, Romesh Kumar-
dc.contributor.authorTalegaonkar, Mrunmay-
dc.contributor.authorElkholy, Ahmed-
dc.contributor.authorAnand, Tejasvi-
dc.contributor.authorKim, Seong Joong-
dc.contributor.authorChoi, Woo Seok-
dc.contributor.authorHanumolu, Pavan Kumar-
dc.date.accessioned2024-05-17T07:39:13Z-
dc.date.available2024-05-17T07:39:13Z-
dc.date.created2024-05-17-
dc.date.issued2015-08-
dc.identifier.citationIEEE Symposium on VLSI Circuits, Digest of Technical Papers, pp.C352-C353-
dc.identifier.urihttps://hdl.handle.net/10371/203199-
dc.description.abstractA low power 14Gb/s transceiver using partially segmented voltage-mode driver, charge-based analog front-end, and low power clock and data recovery circuit that also minimizes clock distribution power is presented. Fabricated in a 65nm CMOS process, the transceiver achieves a power efficiency of 2.8mW/Gb/s and BER<10(-12) while operating at 14Gb/s with 12dB channel loss.-
dc.language영어-
dc.publisherInstitute of Electrical and Electronics Engineers Inc.-
dc.titleA 2.8mW/Gb/s 14Gb/s Serial Link Transceiver in 65nm CMOS-
dc.typeArticle-
dc.identifier.doi10.1109/VLSIC.2015.7231320-
dc.citation.journaltitleIEEE Symposium on VLSI Circuits, Digest of Technical Papers-
dc.identifier.wosid000370961400138-
dc.identifier.scopusid2-s2.0-84957892209-
dc.citation.endpageC353-
dc.citation.startpageC352-
dc.description.isOpenAccessN-
dc.contributor.affiliatedAuthorChoi, Woo Seok-
dc.type.docTypeProceedings Paper-
dc.description.journalClass1-
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  • College of Engineering
  • Department of Electrical and Computer Engineering
Research Area DRAM-PIM, High Bandwidth Memory Interface, O Links, Performance Modeling for I

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