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A 2.8mW/Gb/s 14Gb/s Serial Link Transceiver in 65nm CMOS
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Saxena, Saurabh | - |
dc.contributor.author | Shu, Guanghua | - |
dc.contributor.author | Nandwana, Romesh Kumar | - |
dc.contributor.author | Talegaonkar, Mrunmay | - |
dc.contributor.author | Elkholy, Ahmed | - |
dc.contributor.author | Anand, Tejasvi | - |
dc.contributor.author | Kim, Seong Joong | - |
dc.contributor.author | Choi, Woo Seok | - |
dc.contributor.author | Hanumolu, Pavan Kumar | - |
dc.date.accessioned | 2024-05-17T07:39:13Z | - |
dc.date.available | 2024-05-17T07:39:13Z | - |
dc.date.created | 2024-05-17 | - |
dc.date.issued | 2015-08 | - |
dc.identifier.citation | IEEE Symposium on VLSI Circuits, Digest of Technical Papers, pp.C352-C353 | - |
dc.identifier.uri | https://hdl.handle.net/10371/203199 | - |
dc.description.abstract | A low power 14Gb/s transceiver using partially segmented voltage-mode driver, charge-based analog front-end, and low power clock and data recovery circuit that also minimizes clock distribution power is presented. Fabricated in a 65nm CMOS process, the transceiver achieves a power efficiency of 2.8mW/Gb/s and BER<10(-12) while operating at 14Gb/s with 12dB channel loss. | - |
dc.language | 영어 | - |
dc.publisher | Institute of Electrical and Electronics Engineers Inc. | - |
dc.title | A 2.8mW/Gb/s 14Gb/s Serial Link Transceiver in 65nm CMOS | - |
dc.type | Article | - |
dc.identifier.doi | 10.1109/VLSIC.2015.7231320 | - |
dc.citation.journaltitle | IEEE Symposium on VLSI Circuits, Digest of Technical Papers | - |
dc.identifier.wosid | 000370961400138 | - |
dc.identifier.scopusid | 2-s2.0-84957892209 | - |
dc.citation.endpage | C353 | - |
dc.citation.startpage | C352 | - |
dc.description.isOpenAccess | N | - |
dc.contributor.affiliatedAuthor | Choi, Woo Seok | - |
dc.type.docType | Proceedings Paper | - |
dc.description.journalClass | 1 | - |
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- College of Engineering
- Department of Electrical and Computer Engineering
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