Publications
Detailed Information
A Calibration-Free Fractional-N Ring PLL Using Hybrid Phase/Current-Mode Phase Interpolation Method
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Nandwana, Romesh Kumar | - |
dc.contributor.author | Anand, Tejasvi | - |
dc.contributor.author | Saxena, Saurabh | - |
dc.contributor.author | Kim, Seong-Joong | - |
dc.contributor.author | Talegaonkar, Mrunmay | - |
dc.contributor.author | Elkholy, Ahmed | - |
dc.contributor.author | Choi, Woo Seok | - |
dc.contributor.author | Elshazly, Amr | - |
dc.contributor.author | Hanumolu, Pavan Kumar | - |
dc.date.accessioned | 2024-05-17T07:39:20Z | - |
dc.date.available | 2024-05-17T07:39:20Z | - |
dc.date.created | 2024-05-17 | - |
dc.date.issued | 2015-04 | - |
dc.identifier.citation | IEEE Journal of Solid-State Circuits, Vol.50 No.4, pp.882-895 | - |
dc.identifier.issn | 0018-9200 | - |
dc.identifier.uri | https://hdl.handle.net/10371/203201 | - |
dc.description.abstract | A hybrid phase/current-mode phase interpolator (HPC-PI) is presented to improve phase noise performance of ring oscillator based fractional-N PLLs. The proposed HPC-PI alleviates the bandwidth trade-off between VCO phase noise suppression and Delta Sigma quantization noise suppression. By combining the phase detection and interpolation functions into XOR phase detector/interpolator (XOR PD-PI) block, accurate quantization error cancellation is achieved without using calibration. Use of a digital MDLL in front of the fractional-N PLL helps in alleviating the bandwidth limitation due to reference frequency and enables bandwidth extension even further. The extended bandwidth helps in suppressing the ring-VCO phase noise and lowering the in-band noise floor. Fabricated in 65 nm CMOS process, the prototype generates fractional frequencies from 4.25 to 4.75 GHz, with in-band phase noise floor of -104 dBc/Hz and 1.5 ps(rms) integrated jitter. The clock multiplier achieves power efficiency of 2.4 mW/GHz and FoM of -225.8 dB. | - |
dc.language | 영어 | - |
dc.publisher | Institute of Electrical and Electronics Engineers | - |
dc.title | A Calibration-Free Fractional-N Ring PLL Using Hybrid Phase/Current-Mode Phase Interpolation Method | - |
dc.type | Article | - |
dc.identifier.doi | 10.1109/JSSC.2014.2385756 | - |
dc.citation.journaltitle | IEEE Journal of Solid-State Circuits | - |
dc.identifier.wosid | 000352156000007 | - |
dc.identifier.scopusid | 2-s2.0-85027951195 | - |
dc.citation.endpage | 895 | - |
dc.citation.number | 4 | - |
dc.citation.startpage | 882 | - |
dc.citation.volume | 50 | - |
dc.description.isOpenAccess | Y | - |
dc.contributor.affiliatedAuthor | Choi, Woo Seok | - |
dc.type.docType | Article; Proceedings Paper | - |
dc.description.journalClass | 1 | - |
dc.subject.keywordPlus | DELTA-SIGMA MODULATOR | - |
dc.subject.keywordPlus | FREQUENCY-SYNTHESIZER | - |
dc.subject.keywordPlus | DIGITAL PLL | - |
dc.subject.keywordPlus | CLOCK | - |
dc.subject.keywordAuthor | Calibration-free | - |
dc.subject.keywordAuthor | delta-sigma modulator | - |
dc.subject.keywordAuthor | fractional-N PLL | - |
dc.subject.keywordAuthor | frequency synthesizer | - |
dc.subject.keywordAuthor | multiplying delay-locked loop (MDLL) | - |
dc.subject.keywordAuthor | phase interpolator (PI) | - |
dc.subject.keywordAuthor | phase noise | - |
dc.subject.keywordAuthor | phase-locked loop (PLL) | - |
dc.subject.keywordAuthor | quantization error cancellation | - |
dc.subject.keywordAuthor | ring-VCO | - |
- Appears in Collections:
- Files in This Item:
- There are no files associated with this item.
Related Researcher
- College of Engineering
- Department of Electrical and Computer Engineering
Item View & Download Count
Items in S-Space are protected by copyright, with all rights reserved, unless otherwise indicated.