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A 3.7 mW Low-Noise Wide-Bandwidth 4.5 GHz Digital Fractional-N PLL Using Time Amplifier-Based TDC
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Elkholy, Ahmed | - |
dc.contributor.author | Anand, Tejasvi | - |
dc.contributor.author | Choi, Woo Seok | - |
dc.contributor.author | Elshazly, Amr | - |
dc.contributor.author | Hanumolu, Pavan Kumar | - |
dc.date.accessioned | 2024-05-17T07:39:24Z | - |
dc.date.available | 2024-05-17T07:39:24Z | - |
dc.date.created | 2024-05-17 | - |
dc.date.issued | 2015-04 | - |
dc.identifier.citation | IEEE Journal of Solid-State Circuits, Vol.50 No.4, pp.867-881 | - |
dc.identifier.issn | 0018-9200 | - |
dc.identifier.uri | https://hdl.handle.net/10371/203202 | - |
dc.description.abstract | A digital fractional-N PLL that employs a high resolution TDC and a truly Delta Sigma fractional divider to achieve low in-band noise with a wide bandwidth is presented. The fractional divider employs a digital-to-time converter (DTC) to cancel out Delta Sigma quantization noise in time domain, thus alleviating TDC dynamic range requirements. The proposed digital architecture adopts a narrow range low-power time-amplifier based TDC (TA-TDC) to achieve sub 1 ps resolution. By using TA-TDC in place of a BBPD, the limit cycle behavior that plagues BB-PLLs is greatly suppressed by the TA-TDC, thus permitting wide PLL bandwidth. The proposed architecture is also less susceptible to DTC nonlinearity and has faster settling and tracking behavior compared to a BB-PLL. Fabricated in 65 nm CMOS process, the prototype PLL achieves better than -106 dBc/Hz in-band noise and 3 MHz PLL bandwidth at 4.5 GHz output frequency using 50 MHz reference. The PLL consumes 3.7 mW and achieves better than 490 fs(rms) integrated jitter. This translates to a FoM(J) of -240.5 dB, which is the best among the reported fractional-N PLLs. | - |
dc.language | 영어 | - |
dc.publisher | Institute of Electrical and Electronics Engineers | - |
dc.title | A 3.7 mW Low-Noise Wide-Bandwidth 4.5 GHz Digital Fractional-N PLL Using Time Amplifier-Based TDC | - |
dc.type | Article | - |
dc.identifier.doi | 10.1109/JSSC.2014.2385753 | - |
dc.citation.journaltitle | IEEE Journal of Solid-State Circuits | - |
dc.identifier.wosid | 000352156000006 | - |
dc.identifier.scopusid | 2-s2.0-85027923470 | - |
dc.citation.endpage | 881 | - |
dc.citation.number | 4 | - |
dc.citation.startpage | 867 | - |
dc.citation.volume | 50 | - |
dc.description.isOpenAccess | N | - |
dc.contributor.affiliatedAuthor | Choi, Woo Seok | - |
dc.type.docType | Article; Proceedings Paper | - |
dc.description.journalClass | 1 | - |
dc.subject.keywordPlus | FREQUENCY-SYNTHESIZER | - |
dc.subject.keywordPlus | MHZ BANDWIDTH | - |
dc.subject.keywordPlus | CONVERTER | - |
dc.subject.keywordPlus | CMOS | - |
dc.subject.keywordPlus | TRANSMITTER | - |
dc.subject.keywordPlus | ADPLL | - |
dc.subject.keywordPlus | BIT | - |
dc.subject.keywordAuthor | Phase-locked loops (PLLs) | - |
dc.subject.keywordAuthor | digital PLL | - |
dc.subject.keywordAuthor | ADPLL | - |
dc.subject.keywordAuthor | fractional-N | - |
dc.subject.keywordAuthor | fractional divider | - |
dc.subject.keywordAuthor | frequency synthesizer | - |
dc.subject.keywordAuthor | wide bandwidth | - |
dc.subject.keywordAuthor | BBPD | - |
dc.subject.keywordAuthor | DTC | - |
dc.subject.keywordAuthor | LMS | - |
dc.subject.keywordAuthor | TDC | - |
dc.subject.keywordAuthor | time amplifier | - |
dc.subject.keywordAuthor | jitter | - |
dc.subject.keywordAuthor | digitally controlled oscillator (DCO) | - |
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- College of Engineering
- Department of Electrical and Computer Engineering
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