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8.7 A 4-to-10.5Gb/s 2.2mW/Gb/s continuous-rate digital CDR with automatic frequency acquisition in 65nm CMOS
DC Field | Value | Language |
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dc.contributor.author | Shu, Guanghua | - |
dc.contributor.author | Choi, Woo-Seok | - |
dc.contributor.author | Saxena, Saurabh | - |
dc.contributor.author | Anand, Tejasvi | - |
dc.contributor.author | Elshazly, Amr | - |
dc.contributor.author | Hanumolu, Pavan Kumar | - |
dc.date.accessioned | 2024-05-17T07:39:58Z | - |
dc.date.available | 2024-05-17T07:39:58Z | - |
dc.date.created | 2024-05-17 | - |
dc.date.issued | 2014-02 | - |
dc.identifier.citation | Digest of Technical Papers - IEEE International Solid-State Circuits Conference, Vol.57, pp.150-151 | - |
dc.identifier.issn | 0193-6530 | - |
dc.identifier.uri | https://hdl.handle.net/10371/203212 | - |
dc.description.abstract | Continuous-rate clock-and-data recovery (CDR) circuits with automatic frequency acquisition offer flexibility in both optical and electrical communication networks, and minimize cost with a single-chip multi-standard solution. The two major challenges in the design of such a CDR are: (a) extracting the bit-rate from the incoming random data stream, and (b) designing a wide-tuning-range low-noise oscillator. Among all available frequency detectors (FDs), the stochastic divider-based approach has the widest frequency acquisition range and is well suited for sub-rate CDRs [1]. However, its accuracy strongly depends on input transition density (0 ≤ ρ ≤ 1), with any deviation of ρ from 0.5 (50% transition density) causing 2×(ρ-0.5)×106 ppm of frequency error. In this paper, we present an automatic frequency-acquisition scheme that has unlimited range and is immune to variations in transition density. Implemented using a conventional bang-bang phase detector (BBPD), it requires minimum additional hardware and is applicable to sub-rate CDRs as well. Instead of using multiple LC oscillators that are carefully designed to cover a wide frequency range [2,3], a ring-oscillator-based fractional-N PLL is used as a digitally controlled oscillator (DCO) to achieve both wide range and low noise, and to decouple the tradeoff between jitter transfer (JTRAN) bandwidth and ring-oscillator-noise suppression. © 2014 IEEE. | - |
dc.language | 영어 | - |
dc.publisher | Institute of Electrical and Electronics Engineers Inc. | - |
dc.title | 8.7 A 4-to-10.5Gb/s 2.2mW/Gb/s continuous-rate digital CDR with automatic frequency acquisition in 65nm CMOS | - |
dc.type | Article | - |
dc.identifier.doi | 10.1109/ISSCC.2014.6757377 | - |
dc.citation.journaltitle | Digest of Technical Papers - IEEE International Solid-State Circuits Conference | - |
dc.identifier.wosid | 000353615000055 | - |
dc.identifier.scopusid | 2-s2.0-84898060438 | - |
dc.citation.endpage | 151 | - |
dc.citation.startpage | 150 | - |
dc.citation.volume | 57 | - |
dc.description.isOpenAccess | N | - |
dc.contributor.affiliatedAuthor | Choi, Woo-Seok | - |
dc.type.docType | Conference Paper | - |
dc.description.journalClass | 1 | - |
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- Department of Electrical and Computer Engineering
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