A fast power-on 2.2Gb/s burst-mode digital CDR with programmable input jitter filtering

Abstract

A digital burst-mode CDR employs feed-forward data edge injection and a digital feedback loop to achieve instantaneous phase locking, data-rate tracking, and input jitter filtering. Fabricated in a 90nm CMOS process, the prototype receiver achieves instantaneous locking on the very first data edge and consumes 6.1mW at 2.2Gb/s. By controlling the edge injection rate, the proposed architecture allows variable JTRAN bandwidth from 5MHz to 40MHz. © 2013 JSAP.