A 5Gb/s 2.6mW/Gb/s reference-less half-rate PRPLL-based digital CDR

Abstract

A reference-less half-rate digital CDR implements proportional control in phase domain with a phase-rotating PLL (PRPLL) which decouples jitter transfer (JTRAN) bandwidth and jitter tolerance (JTOL) corner frequency, eliminates jitter peaking, and removes JTRAN dependence on phase detector gain. Fabricated in a 90nm CMOS process, the prototype CDR achieves 2MHz JTRAN, 16MHz JTOL, and consumes 13.1mW from 1V supply at 5Gb/s with BER<10-12. © 2013 JSAP.