Reduction in energy consumption by bootstrapped n MOS switches inreversible adiabatic CMOS circuits

Abstract

For ultra-low-energy applications, hootstrapped reversible-energy-re cove^ logic (bRERL) is proposed, which is a reversible adiabatic CMOS logic and requires an 8-phase clock. In hRERL, each transmission gate was replaced by a bootstrapped nMOS switch in the logic functional blocks of tRERI,. Using SPICE simulations, it was confirmed that the bRERL circuit consumed less energy and occupied less area than the tRERL circuit. The authors integrated a hRERL inverter chain with its 8-phase, clocked power generator in a test chip, which was fabricated with 0 . 6 C~M OS technology. They also confirmed that they could minimise the energy consumption in the hRERL circuit by reducing the operating frequency until adiabatic and leakage losses were equal.