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A mixed-level virtual prototyping environment for SystemC-based design methodology

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dc.contributor.authorPark, Sanggyu-
dc.contributor.authorYoon, Sangyong-
dc.contributor.authorChae, Soo-Ik-
dc.date.accessioned2009-12-17T05:55:25Z-
dc.date.available2009-12-17T05:55:25Z-
dc.date.issued2009-
dc.identifier.citationMicroelectronics Journal. 40(7) 1082-1093.en
dc.identifier.issn0026-2692-
dc.identifier.urihttps://hdl.handle.net/10371/21264-
dc.description.abstractWeproposeaflexiblemixed-levelvirtualprototypingenvironment,wheremodelsindifferent
abstraction levelssuchastransactionlevel,register-transferlevel,andsoftwarelevelcanbeco-
simulatedtogether.Intheproposedenvironment,thedesignersshouldcaptureatransactionlevel
systemmodelbeforehardware–softwarepartitioning,fromwhichmixed-levelvirtualprototyping
models canberefinedwithpre-definedandpre-verifiedcommunicationprimitives.Weexplainseveral
techniquesemployedintheenvironmentsuchasIDportsforsoftwaretemplateefficiency,abstraction
adaptersinSystemCformixedlevelsimulation,andtrace-drivensimulationforfasterperformance
evaluation.Moreover,transactionleveldescriptionsinSystemCcanbecompiledandexecutedas
softwaretogetherwiththeDEOS,whichisanoperatingsystemthatprovidesSystemCAPIs.We
comparedthesimulationspeedofseveralmixed-levelvirtualprototypesofaH.264decodertoshowthe
effectiveness oftheproposedenvironment.
en
dc.language.isoen-
dc.publisherElsevieren
dc.subjectSystemCen
dc.subjectTransactionlevelmodelen
dc.subjectChannelen
dc.subjectArchitecturetemplateen
dc.subjectVirtual prototypeen
dc.titleA mixed-level virtual prototyping environment for SystemC-based design methodologyen
dc.typeArticleen
dc.contributor.AlternativeAuthor박상규-
dc.contributor.AlternativeAuthor윤상용-
dc.contributor.AlternativeAuthor채수익-
dc.identifier.doi10.1016/j.mejo.2008.05.010-
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