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Cache Optimization for H.264/AVC Motion Compensation

DC Field Value Language
dc.contributor.authorYoon, Sangyong-
dc.contributor.authorChae, Soo-Ik-
dc.date.accessioned2009-12-18T05:56:11Z-
dc.date.available2009-12-18T05:56:11Z-
dc.date.issued2008-12-
dc.identifier.citationIEICE Trans. Information and Systems, vol. E91-D no. 12 pp.2902-2905en
dc.identifier.issn0916-8532-
dc.identifier.urihttps://hdl.handle.net/10371/21377-
dc.description.abstractIn this letter, we propose a cache organization that substantially
reduces the memory bandwidth of motion compensation (MC) in
the H.264/AVC decoders. To reduce duplicated memory accesses to P and
B pictures, we employ a four-way set-associative cache in which its index
bits are composed of horizontal and vertical address bits of the frame buffer
and each line stores an 8 × 2 pixel data in the reference frames. Moreover,
we alleviate the data fragmentation problem by selecting its line size that
equals the minimum access size of the DDR SDRAM. The bandwidth of
the optimized cache averaged over five QCIF IBBP image sequences requires
only 129% of the essential bandwidth of an H.264/AVC MC.
en
dc.language.isoen-
dc.publisherInstitute of Electronics, Information and Communication Engineersen
dc.subjectcacheen
dc.subjectH.264en
dc.subjectmotion compensationen
dc.subjectmemory bandwidthen
dc.subjectDDRen
dc.titleCache Optimization for H.264/AVC Motion Compensationen
dc.typeArticleen
dc.contributor.AlternativeAuthor윤상용-
dc.contributor.AlternativeAuthor채수익-
Appears in Collections:
College of Engineering/Engineering Practice School (공과대학/대학원)Dept. of Electrical and Computer Engineering (전기·정보공학부)Journal Papers (저널논문_전기·정보공학부)
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