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Cache Optimization for H.264/AVC Motion Compensation
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Yoon, Sangyong | - |
dc.contributor.author | Chae, Soo-Ik | - |
dc.date.accessioned | 2009-12-18T05:56:11Z | - |
dc.date.available | 2009-12-18T05:56:11Z | - |
dc.date.issued | 2008-12 | - |
dc.identifier.citation | IEICE Trans. Information and Systems, vol. E91-D no. 12 pp.2902-2905 | en |
dc.identifier.issn | 0916-8532 | - |
dc.identifier.uri | https://hdl.handle.net/10371/21377 | - |
dc.description.abstract | In this letter, we propose a cache organization that substantially
reduces the memory bandwidth of motion compensation (MC) in the H.264/AVC decoders. To reduce duplicated memory accesses to P and B pictures, we employ a four-way set-associative cache in which its index bits are composed of horizontal and vertical address bits of the frame buffer and each line stores an 8 × 2 pixel data in the reference frames. Moreover, we alleviate the data fragmentation problem by selecting its line size that equals the minimum access size of the DDR SDRAM. The bandwidth of the optimized cache averaged over five QCIF IBBP image sequences requires only 129% of the essential bandwidth of an H.264/AVC MC. | en |
dc.language.iso | en | - |
dc.publisher | Institute of Electronics, Information and Communication Engineers | en |
dc.subject | cache | en |
dc.subject | H.264 | en |
dc.subject | motion compensation | en |
dc.subject | memory bandwidth | en |
dc.subject | DDR | en |
dc.title | Cache Optimization for H.264/AVC Motion Compensation | en |
dc.type | Article | en |
dc.contributor.AlternativeAuthor | 윤상용 | - |
dc.contributor.AlternativeAuthor | 채수익 | - |
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