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Vertical AND-Type Flash Synaptic Cell Stack for High-Density and Reliable Binary Neural Networks

Cited 4 time in Web of Science Cited 4 time in Scopus
Authors

Kim, Jangsaeng; Im, Jiseong; Oh, Seongbin; Shin, Wonjun; Jung, Gyuweon; Lee, Sung-Tae; Lee, Jong-Ho

Issue Date
2024-07
Publisher
Institute of Electrical and Electronics Engineers
Citation
IEEE Electron Device Letters, Vol.45 No.7, pp.1369-1372
Abstract
A vertical AND-type (V-AND) cell stack consisting of flash memory cells is proposed and fabricated for hardware-based binary neural networks (BNNs). Low-power operation is possible with a semicircular poly-Si channel surrounded by a single word-line. In each floor, two cells facing each other along the long axis of a single channel hole share a source/drain, greatly improving cell density and making it suitable for high-density BNNs. The fabricated V-AND flash memory cells show a high on/off current ratio (> 10(5)), sub-pA off current, and large dynamic range (> 10(4)). One-shot patterning of channel holes and isolation trenches minimizes loss of uniformity due to misalignment. The proposed BNN using synaptic properties measured from fabricated V-AND cells achieves high accuracy (87.82% for the CIFAR-10 dataset).
ISSN
0741-3106
URI
https://hdl.handle.net/10371/217494
DOI
https://doi.org/10.1109/LED.2024.3401399
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Research Area Integrated systems of silicon-based logic-memory-sensors, Low-power semiconductor-type sensor platforms, Semiconductor materials and devices, 반도체 재료 및 소자, 실리콘 로직-메모리-센서 집적 시스템, 저전력 반도체 센서 플랫폼

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