Novel XNOR-based approximate computing for energy-efficient image processors

Abstract

Approximate computing, which has a trade-off between accuracy and performance, has emerged as a promising solution for energy-efficient designs in error-tolerant applications. In this paper, the design of a novel approximate adder and multiplier is studied and proposed. First, a new approximate adder based on XNOR gates and a hybrid adder using them to reduce the error rate is proposed. Then, a new high-performance and energy-efficient approximate binary multiplier with acceptable error metrics is investigated. The proposed multiplier shows better error metrics than other previous approximate multipliers and significantly improvements area, delay, and power consumption by up to 20% compared to the exact binary multiplier. Finally, we apply the approximate binary multipliers to the JPEG encoder and achieve a significant reduction in the area, speed, and power consumption with a negligible quality loss of the output image. So, the proposed approximate arithmetic computing logics are suitable for high-performance and energy-efficient hardware designs.