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Issue Date	Title / Author(s) / Citation	File
2019-03	56Gb/s PAM-4 VCSEL Transmitter With Quarter-Rate Forwarded Clock Using 65nm CMOS Circuits Hwang, Jeongho; Do, Hyungrok; Choi, Hong-Seok; Jeong, Gyu-Seob; Koh, Daehyun; Kim, Sungwoo; Jeong, Deog-Kyoon 2019 OPTICAL FIBER COMMUNICATIONS CONFERENCE AND EXHIBITION (OFC), p. 18618476
2019-06	A 64Gb/s 2.29pJ/b PAM-4 VCSEL Transmitter With 3-Tap Asymmetric FFE in 65nm CMOS Hwang, Jeongho; Choi, Hong-Seok; Do, Hyungrok; Jeong, Gyu-Seob; Koh, Daehyun; Park, Kwanseo; Kim, Sungwoo; Jeong, Deog-Kyoon 2019 SYMPOSIUM ON VLSI CIRCUITS, pp.C268-C269	DOI
2022-06	A Low-Jitter 8-GHz RO-Based ADPLL With PVT-Robust Replica-Based Analog Closed Loop for Supply Noise Compensation Kim, Hyojun; Jung, Woosong; Kim, Kwandong; Kim, Sungwoo; Choi, Woo-Seok; Jeong, Deog-Kyoon IEEE Journal of Solid-State Circuits, Vol.57 No.6, pp.1712-1722	DOI
2022-06	A 2.5 -32 Gb/s Gen 5-PCIe Receiver with Multi-Rate CDR Engine and Hybrid DFE Choi, Moon-Chul; Lee, Sanghee; Roh, Seungha; Lee, Kwangho; Oh, Jonghyun; Kim, Sungwoo; Kim, Kwandong; Choi, Woo-Seok; Kim, Jaeha; Jeong, Deog-Kyoon IEEE Transactions on Circuits and Systems II: Express Briefs, Vol.69 No.6, pp.2677-2681	DOI