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아날로그 싱크로너스 미러 딜레이 기법을 이용한 고속 locking 특성을 갖는 동기시스템의 설계 : A Design of fast locking clock generator using analog synchronous mirror delay technique for high speed DRAM application
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- Authors
- Advisor
- 김원찬
- Issue Date
- 2000
- Publisher
- 서울대학교 대학원
- Keywords
- 클럭 발생기 ; clock cynchronization ; synchronous mirror delay (SMD) ; comparator ; locking ; fast locking ; duty cycle corrector ; static phase error
- Description
- 학위논문(박사)--서울대학교 대학원 :전기공학부,2000.
- Language
- Korean
- URI
- http://dcollection.snu.ac.kr:80/jsp/common/DcLoOrgPer.jsp?sItemId=000000069161
https://hdl.handle.net/10371/30912
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