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Design of an All-Digital Delay-Locked Loop using a Successive Approximation Register : 연속 근사 레지스터를 이용한 All-Digital Delay-Locked Loop의 설계

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Authors

Guillaume, Weill

Advisor
정덕균
Issue Date
2009
Publisher
서울대학교 대학원
Keywords
All-digitalDelay-locked loopClock managementDigitalizationDuty-cycle correction
Description
Thesis(masters) --서울대학교 대학원 :전기. 컴퓨터공학부, 2009.2.
Language
English
URI
http://dcollection.snu.ac.kr:80/jsp/common/DcLoOrgPer.jsp?sItemId=000000037111

https://hdl.handle.net/10371/44694
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