Publications
Detailed Information
Power reduction in look-up table based FPGAs by glitch minimization
Cited 0 time in
Web of Science
Cited 0 time in Scopus
- Authors
- Advisor
- 장래혁
- Issue Date
- 2005
- Publisher
- 서울대학교 대학원
- Keywords
- FPGA ; 저전력 ; power-reduction ; 최적화 ; optimization ; NP-complete ; NP-complete ; 시뮬레이션 ; simulation
- Description
- Thesis(master`s)--서울대학교 대학원 :전기.컴퓨터공학부,2005.
- Language
- English
- URI
- http://dcollection.snu.ac.kr:80/jsp/common/DcLoOrgPer.jsp?sItemId=000000052883
https://hdl.handle.net/10371/50027
- Files in This Item:
- There are no files associated with this item.
Item View & Download Count
Items in S-Space are protected by copyright, with all rights reserved, unless otherwise indicated.