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College of Engineering/Engineering Practice School (공과대학/대학원)
Dept. of Electrical and Computer Engineering (전기·정보공학부)
Theses (Master's Degree_전기·정보공학부)
Clock generation circuit with all-digital PLL
디지털 PLL을 이용한 clock 발생용 회로에 관한 연구
- Authors
- 안현석
- Advisor
- 정덕균
- Issue Date
- 2007
- Publisher
- 서울대학교 대학원
- Keywords
- All -digital PLL(ADPLL); All -digital PLL; DCO(Digitally Controlled Oscillator); Digitally Controlled Oscillator; TDC(Time-to-Digital Converter); Time-to-Digital Converter; Delta-Sigma Modulator; Delta-Sigma Modulator; 위상잡음; Phase noise; Jitter
- Description
- 학위논문(석사) --서울대학교 대학원 :전기. 컴퓨터공학부,2007.
- Language
- Korean
- URI
- http://dcollection.snu.ac.kr:80/jsp/common/DcLoOrgPer.jsp?sItemId=000000043911
http://hdl.handle.net/10371/52469
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