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성능 개선을 위한 이중게이트 구조 단전자 트랜지스터의 공정 방법 : Fabrication process of dual gate structured single-electron transistors for performance improvement
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- Authors
- Advisor
- 이종덕
- Issue Date
- 2007
- Publisher
- 서울대학교 대학원
- Keywords
- 단전자 트랜지스터 ; Single-Electron Transistor ; 이중게이트 구조 ; Dual-Gate Structure ; tunneling 장벽 ; tunneling barrier ; self-align ; self-align ; 공정방법 ; fabrication process
- Description
- 학위논문(석사) --서울대학교 대학원 :전기. 컴퓨터공학부,2007.
- Language
- Korean
- URI
- http://dcollection.snu.ac.kr:80/jsp/common/DcLoOrgPer.jsp?sItemId=000000043851
https://hdl.handle.net/10371/52484
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