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College of Engineering/Engineering Practice School (공과대학/대학원)
Dept. of Electrical and Computer Engineering (전기·정보공학부)
Theses (Master's Degree_전기·정보공학부)
저전력을 고려한 재구성형 프로세싱 시스템의 최적화
Power-conscious optimization of coarse-grained reconfigurable architecture
- Authors
- 박일현
- Advisor
- 최기영
- Issue Date
- 2007
- Publisher
- 서울대학교 대학원
- Keywords
- 시스템 온 칩; System-on-Chip (SoC); 저전력; Low Power; 재구성형 프로세싱 시스템; Coarse-Grained Reconfigurable Architecture (CGRA); 콘피규레이션 캐시; Configuration Cache; 루프 파이프라이닝; Loop Pipelining; Context Pipelining; Context Pipelining; Temporal 매핑; Temporal Mapping; Spatial 매핑; Spatial Mapping; Processing Element; Processing Element
- Description
- 학위논문(석사) --서울대학교 대학원 :전기. 컴퓨터공학부,2007.
- Language
- Korean
- URI
- http://dcollection.snu.ac.kr:80/jsp/common/DcLoOrgPer.jsp?sItemId=000000043897
http://hdl.handle.net/10371/52514
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