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Fabrication and analysis of Si-through-via for stacked wafer-level MEMS packaging : MEMS 소자의 적층형 웨이퍼 수준 실장을 위한 실리콘 관통 비아의 제작 및 해석
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- Authors
- Advisor
- 전국진
- Issue Date
- 2007
- Publisher
- 서울대학교 대학원
- Keywords
- 관통 비아 ; Through-via ; 3차원 MEMS 소자 ; 3D MEMS devices ; MEMS 패키지 ; MEMS package ; 3차원 센서 ; 3D sensor ; 적층형 패키지 ; stacked package ; SiP ; SiP
- Description
- Thesis(master`s)--서울대학교 대학원 :전기·컴퓨터공학부,2007.
- Language
- English
- URI
- http://dcollection.snu.ac.kr:80/jsp/common/DcLoOrgPer.jsp?sItemId=000000045787
https://hdl.handle.net/10371/53536
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