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A Compiler-Friendly RISC-Based Digital Signal Processor Synthesis and Performance Evaluation
Cited 3 time in
Web of Science
Cited 3 time in Scopus
- Authors
- Issue Date
- 2001-03
- Publisher
- Springer Verlag
- Citation
- Journal of VLSI Signal Processing, 2001, vol. 27, no. 3, pp. 297-312
- Keywords
- digital signal processor ; code converter ; compiler-friendly ; architecture synthesis ; performance evaluation
- Abstract
- As DSP (Digital Signal Processing) applications become more complex, there is also a growing need
for new architectures supporting efficient high-level language compilers. We try to synthesize a new DSP processor
architecture by adding several DSP processor specific features to a RISC core that has a compiler friendly structure,
such asmany general-purpose registers and orthogonal instructions. The synthesized digital signal processor supports
single-cycleMAC (Multiply-and-ACcumulate), direct memory access, automatic address generation, and hardware
looping capabilities in addition to ordinary RISC instructions. The compiler for the new architecture is quickly
implemented by developing a code-converter that modifies the assembly codes that are generated by the RISC
compiler. The performance effects of adding each of these as well as all the combined features are evaluated using
seven DSP-kernel benchmarks, aQCELPvocoder, and anMPEGvideo decoder. The effects ofCPUclock frequency
change due to the addition of these features are also considered. Finally, we also compare the performances with
several existing DSP processors, such as TMS320C3x, TMS320C54x, and TMS320C5x.
- ISSN
- 0922-5773 (print)
1573-109X (online)
- Language
- English
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