S-Space College of Engineering/Engineering Practice School (공과대학/대학원) Dept. of Electrical and Computer Engineering (전기·정보공학부) Others_전기·정보공학부
VLSI implementation of a soft bit-flipping decoder for PG-LDPC codes
- Cho, Junho; Kim, Jonghong; Ji, Hyunwoo; Sung, Wonyong
- Issue Date
- IEEE International Symposium on Circuits and Systems (ISCAS), pp. 908-911, May 2009
- Implementation of high throughput VLSI chips for low-density parity-check codes has been considered very difficult especially when the row or column weight of the code is high. In this paper, a projective-geometry (PG) LDPC code is implemented in VLSI employing the proposed soft bit flipping (SBF) algorithm. The SBF algorithm requires only simple interconnections, but its error correcting performance is close to the sum-product algorithm (SPA). Parallel processing architecture is employed for increasing the throughput. With the (1057, 813) PG-LDPC code, the implemented 4-bit SBF decoder consumes only a small area of 2.5mm2 while providing 6.5Gbps and good performance close to the floating-point SPA by 0.6dB at the frame error rate of 10-4.
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