S-Space College of Engineering/Engineering Practice School (공과대학/대학원) Dept. of Electrical and Computer Engineering (전기·정보공학부) Journal Papers (저널논문_전기·정보공학부)
Fixed-point error analysis and word length optimization of 8 x 8 IDCT architectures
- Kim, Seehyun; Sung, Wonyong
- Issue Date
- IEEE Trans. Circuits and Systems for Video Technology, vol. 8, no. 8, pp. 935-940, Dec. 1998
- Distributed arithmetic; fixed-point error analysis; IDCT; IEEE Standard 1180-1990; word length optimization
- Complete fixed-point error models that include the coefficient quantization are derived for two popular 8×8 two-dimensional (2-D) IDCT architectures; one is based on distributed arithmetic, and the other is the multiplier-adder chain. The error models are evaluated in the integer domain to accurately measure the effects of rounding. The analysis results show that the overall mean-square error performance (OMSE) is the most critical condition for meeting the IEEE specification (IEEE Std. 1180-1990) when the rounding scheme is employed. On the other hand, the mean error effects (OME and PME) are dominant for truncation. Finally, the analysis results are compared with those of bit-accurate simulation.
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