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Power Efficient Architectures for VSELP Speech Coders
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Gu, Zhenzhong | - |
| dc.contributor.author | Sudhakar, R. | - |
| dc.contributor.author | Lee, Kwang Bok | - |
| dc.date.accessioned | 2010-04-09T06:40:47Z | - |
| dc.date.available | 2010-04-09T06:40:47Z | - |
| dc.date.issued | 1997-09 | - |
| dc.identifier.citation | Electronics Letters- IEE, vol. 33, pp. 1682-1683 | en |
| dc.identifier.issn | 0013-5194 | - |
| dc.identifier.uri | https://hdl.handle.net/10371/62870 | - |
| dc.description.abstract | The authors summarise the findings of a feasibility study conducted to evaluate parallel implemenations of a VSELP speech coder in digital radio. | en |
| dc.description.sponsorship | This work was supported by a grant from Motorola, Inc. | en |
| dc.language.iso | en | en |
| dc.publisher | Institution of Engineering and Technology | en |
| dc.subject | speech coding | en |
| dc.subject | digital signal processing | en |
| dc.title | Power Efficient Architectures for VSELP Speech Coders | en |
| dc.type | Article | en |
| dc.contributor.AlternativeAuthor | 이광복 | - |
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