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시간 제약을 고려하는 플립칩 설계에서 Boolean SAT를 활용한 라우팅 기법
Timing constrained routing in IO area flip chip design based on Boolean Satisfiability

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Authors
전형준
Advisor
김태환
Issue Date
2010
Publisher
서울대학교 대학원
Keywords
플립칩 라우팅flip chip routing시간 제약timing constrainBoolean SATBoolean SAT
Description
학위논문(석사) --서울대학교 대학원 :전기. 컴퓨터공학부,2010.2.
Language
Korean
URI
http://dcollection.snu.ac.kr:80/jsp/common/DcLoOrgPer.jsp?sItemId=000000033502

https://hdl.handle.net/10371/64990
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College of Engineering/Engineering Practice School (공과대학/대학원)Dept. of Electrical and Computer Engineering (전기·정보공학부)Theses (Master's Degree_전기·정보공학부)
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