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시간 제약을 고려하는 플립칩 설계에서 Boolean SAT를 활용한 라우팅 기법 : Timing constrained routing in IO area flip chip design based on Boolean Satisfiability
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- Authors
- Advisor
- 김태환
- Issue Date
- 2010
- Publisher
- 서울대학교 대학원
- Keywords
- 플립칩 라우팅 ; flip chip routing ; 시간 제약 ; timing constrain ; Boolean SAT ; Boolean SAT
- Description
- 학위논문(석사) --서울대학교 대학원 :전기. 컴퓨터공학부,2010.2.
- Language
- Korean
- URI
- http://dcollection.snu.ac.kr:80/jsp/common/DcLoOrgPer.jsp?sItemId=000000033502
https://hdl.handle.net/10371/64990
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