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College of Engineering/Engineering Practice School (공과대학/대학원)
Dept. of Electrical and Computer Engineering (전기·정보공학부)
Theses (Master's Degree_전기·정보공학부)
지연시간 편차를 고려한 클락 버퍼 위상 지정 기법
Clock Buffer Polarity Assignment Considering the Effect of Delay Variations
- Authors
- 강민석
- Advisor
- 김태환
- Issue Date
- 2010
- Publisher
- 서울대학교 대학원
- Keywords
- 클락 트리; clock tree; 시간 편차; timing variation; 전원 노이즈; power; 회로 최적화; ground noise; optimization circuits
- Description
- 학위논문(석사) --서울대학교 대학원 :전기. 컴퓨터공학부,2010.2.
- Language
- Korean
- URI
- http://dcollection.snu.ac.kr:80/jsp/common/DcLoOrgPer.jsp?sItemId=000000033417
http://hdl.handle.net/10371/65223
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