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Investigation of various copper seed layers for copper electrodeposition applicable to ultralarge-scale integration interconnection
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Kim, Jae Jeong | - |
dc.contributor.author | Kim, Soo-Kil | - |
dc.contributor.author | Lee, Chang Hwa | - |
dc.contributor.author | Kim, Yong Shik | - |
dc.date.accessioned | 2010-05-12T04:42:20Z | - |
dc.date.available | 2010-05-12T04:42:20Z | - |
dc.date.issued | 2002-12-16 | - |
dc.identifier.citation | The Journal of Vacuum Science and Technology B Microelectronics and Nanometer Structures 21, 33-38 | en |
dc.identifier.issn | 1071-1023 | - |
dc.identifier.uri | https://hdl.handle.net/10371/65979 | - |
dc.description.abstract | As a superior substituent for the chemical-vapor deposition and physical-vapor deposition ~PVD!
Cu processes in an ultralarge-scale integrated interconnection, electrodeposition on two kinds of electroless-plated Cu seed layers was investigated. Co~II! and formaldehyde were used as reducing agents for each electroless plating. Two samples of electroless-plated seed layers had relatively higher resistivity due to rough and irregular grains and weakly developed ~111! texture, which are peculiarities of electroless plating. However, the Cu electrodeposited onto the electroless-plated seed showed reasonably good characteristics in resistivity, impurity level, crystalline structure, and surface roughness compared to those on the conventional PVD Cu seed. For the gap filling in the damascene structure, the electroless seed layer plating using formaldehyde and the subsequent electrodeposition on a patterned wafer showed an excellent filling profile without any voids or keyholes. After 400 °C annealing in a N2 atmosphere, adhesion between the Cu/barrier interfaces of electrodeposited copper on the two electroless-plated seeds was highly improved. | en |
dc.language.iso | en | en |
dc.publisher | American Vacuum Society | en |
dc.subject | copper | en |
dc.subject | electrodeposition | en |
dc.subject | circuit interconnections | en |
dc.subject | electroless deposited coatings | en |
dc.subject | electrodeposits | en |
dc.subject | electrical resistivity | en |
dc.subject | metallic thin films | en |
dc.subject | surface topography | en |
dc.subject | organic compounds | en |
dc.subject | annealing | en |
dc.subject | adhesion | en |
dc.subject | integrated circuit metallisation | en |
dc.title | Investigation of various copper seed layers for copper electrodeposition applicable to ultralarge-scale integration interconnection | en |
dc.type | Article | en |
dc.contributor.AlternativeAuthor | 김재정 | - |
dc.contributor.AlternativeAuthor | 김수길 | - |
dc.contributor.AlternativeAuthor | 이창화 | - |
dc.contributor.AlternativeAuthor | 김용식 | - |
dc.identifier.doi | 10.1116/1.1529654 | - |
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