S-Space College of Engineering/Engineering Practice School (공과대학/대학원) Dept. of Electrical and Computer Engineering (전기·정보공학부) Journal Papers (저널논문_전기·정보공학부)
A 0.25-μm CMOS 1.9-GHz PHS RF Transceiver With a 150-kHz Low-IF Architecture
- Jeong, Hoesam; Yoo, Byoung-Joo; Han, Cheolkyu; Lee, Sang-Yoon; Lee, Kang-Yoon; Kim, Suhwan; Jeong, Deog-Kyoon; Kim, Wonchan
- Issue Date
- IEEE Journal of Solid State Circuits, vol. 42, no. 6, pp. 1318-1327
- We present a 1.9-GHz Personal Handy-phone System (PHS) transceiver, fully integrated and fabricated in 0.25-mum CMOS technology. The receiver is based on a 150-kHz low-IF architecture and meets the fast channel switching and DC-offset cancellation requirements of PHS. It includes a low-noise amplifier (LNA), a downconversion mixer, a complex filter, and a programmable gain amplifier. A fractional-N frequency synthesizer achieves seamless handover with a 25 mus channel switching time and a phase noise of -121 dBc/Hz at a 600-kHz offset frequency, with compliant ACS performance. The receiver provides -105 dBm sensitivity and 55 dBc ACS at a 600-kHz frequency offset. The transmitter is based on the direct modulation architecture and consists of an upconversion mixer and a pre-driver stage. The gain of the pre-driver is digitally controllable to suit any type of commercial power amplifier. The transmitter shows a 3% EVM and a 65 dBc ACPR at a 600-kHz offset frequency. The whole transceiver occupies 15.2 mm2 and dissipates 70 mA in RX and 44 mA in TX, with a 2.8-V supply.
- Files in This Item: There are no files associated with this item.