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Low-Power Implementation of a High-Throughput LDPC Decoder for IEEE 802.11n Standard

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Authors
Cho, Junho; Shanbhag, Naresh R.; Sung, Wonyong
Issue Date
2009-10
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Citation
IEEE Workshop on Signal Processing Systems, 7-9 Oct. 2009, Tampere, Finland, pp. 40-45
Abstract
A flexible and scalable LDPC decoder architecture is developed for the IEEE 802.11n standard. A serial-parallel architecture is employed for achieving high throughput with low chip area, and triple-bank memory blocks are used for parallel factor expansion. Two low-power strategies using voltage over-scaling (VOS) and reduced-precision replica (RPR) are applied to the decoder. Power saving of up to 35% is demonstrated when implemented in a 90nm CMOS technology.
ISSN
1520-6130
Language
English
URI
https://hdl.handle.net/10371/69746
DOI
https://doi.org/10.1109/SIPS.2009.5336223
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College of Engineering/Engineering Practice School (공과대학/대학원)Dept. of Electrical and Computer Engineering (전기·정보공학부)Others_전기·정보공학부
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