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Low-Power Implementation of a High-Throughput LDPC Decoder for IEEE 802.11n Standard
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Cited 6 time in Scopus
- Authors
- Issue Date
- 2009-10
- Citation
- IEEE Workshop on Signal Processing Systems, 7-9 Oct. 2009, Tampere, Finland, pp. 40-45
- Abstract
- A flexible and scalable LDPC decoder architecture is developed for the IEEE 802.11n standard. A serial-parallel architecture is employed for achieving high throughput with low chip area, and triple-bank memory blocks are used for parallel factor expansion. Two low-power strategies using voltage over-scaling (VOS) and reduced-precision replica (RPR) are applied to the decoder. Power saving of up to 35% is demonstrated when implemented in a 90nm CMOS technology.
- ISSN
- 1520-6130
- Language
- English
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