A true single-phase energy-recovery multiplier

Abstract

In this paper, we present the design and experimental evaluation of an 8-bit energy-recovery multiplier with built-in self-test logic and an internal single-phase sinusoidal power-clock generator. Both the multiplier and the built-in self-test have been designed in SCAL-D, a true single-phase adiabatic logic family. Fabricated in a 0.5- m standard n-well CMOS process, the chip has an active area of 0.47 mm2. Correct chip operation has been verified for clock rates up to 140 MHz. Moreover, chip dissipation measurements correlate well with HSPICE simulation results. For a selection of biasing conditions that yield correct operation at 140 MHz, total measured average dissipation for the multiplier and the power-clock generator is 250 pJ per operation. Index Terms—Adiabatic design, arithmetic circuits, charge recovery, dynamic circuits, LC tank circuits, low-energy circuits, low-power circuits, very large scale integration (VLSI) design.