S-Space College of Engineering/Engineering Practice School (공과대학/대학원) Dept. of Electrical and Computer Engineering (전기·정보공학부) Journal Papers (저널논문_전기·정보공학부)
A true single-phase energy-recovery multiplier
Cited 34 time in Web of Science Cited 47 time in Scopus
- Issue Date
- IEEE Transactions on Very Large Scale Integration Systems, vol. 11, no. 2, pp. 194-207
- Adiabatic design ; arithmetic circuits ; charge recovery ; dynamic circuits ; LC tank circuits ; low-energy circuits ; low-power circuits ; very large scale integration (VLSI) design
- In this paper, we present the design and experimental
evaluation of an 8-bit energy-recovery multiplier with built-in
self-test logic and an internal single-phase sinusoidal power-clock
generator. Both the multiplier and the built-in self-test have been
designed in SCAL-D, a true single-phase adiabatic logic family.
Fabricated in a 0.5- m standard n-well CMOS process, the chip
has an active area of 0.47 mm2. Correct chip operation has been
verified for clock rates up to 140 MHz. Moreover, chip dissipation
measurements correlate well with HSPICE simulation results. For
a selection of biasing conditions that yield correct operation at 140
MHz, total measured average dissipation for the multiplier and
the power-clock generator is 250 pJ per operation.
Index Terms—Adiabatic design, arithmetic circuits, charge
recovery, dynamic circuits, LC tank circuits, low-energy circuits,
low-power circuits, very large scale integration (VLSI) design.
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