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Power Reduction Technique in Coefficient Multiplications Through Multiplier Characterization
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- Authors
- Issue Date
- 2004
- Publisher
- Springer Verlag
- Citation
- Journal of VLSI Signal Processing Systems, vol. 38, no. 2, pp. 101-113
- Abstract
- This paper presents a multiplier power reduction technique for low-power DSP applications through
utilization of coefficient optimization. The optimization is implementation dependent in that the multipliers are
assumed to be designed in either ASIC or full-custom architectures for general purpose multiplication. The paper
first describes a model characterizing the power consumption of the multiplier. Then the coefficient optimized made
based on this model. This methodology is applicable to multiplications requiring a large set of coefficients and
random data sets.We can accurately estimate the actual power dissipation of the multipliers using the characterization
technique. The coefficient optimization based on the power model can save as much as 34.02%.
- Language
- English
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