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Efficient Hardware Controller Synthesis for Synchronous Dataflow Graph in System Level Design

Cited 13 time in Web of Science Cited 16 time in Scopus
Authors
Jung, Hyunuk; Lee, Kangnyoung; Ha, Soonhoi
Issue Date
2002-08
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Citation
IEEE Transactions on Very Large Scale Integration(VLSI) Systems, Vol. 10, No. 4, pp. 423-428, 2002
Keywords
Data flow graphsynchronous data flowsystem level designVHDL
Abstract
Abstract—This paper concerns automatic hardware synthesis
from data flow graph (DFG) specification in system level design. In
the presented design methodology, each node of a data flow graph
represents a hardware library module that contains a synthesizable
VHDL code. Our proposed technique automatically synthesizes a
clever control structure, cascaded counter controller, that supports
asynchronous interaction with outside modules while efficiently
implementing the synchronous dataflow semantics of the graph
at the same time. Through comparison with previous works with
some examples, the novelty of the proposed technique is demonstrated.
ISSN
1063-8210
Language
English
URI
http://hdl.handle.net/10371/7987
DOI
https://doi.org/10.1109/TVLSI.2002.807765
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College of Engineering/Engineering Practice School (공과대학/대학원)Dept. of Computer Science and Engineering (컴퓨터공학부)Journal Papers (저널논문_컴퓨터공학부)
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