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VLSI Implementation of a VC-1 Main Profile Decoder for HD Video Applications
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Cho, Jinhyun | - |
dc.contributor.author | Yoon, Sangyong | - |
dc.contributor.author | Park, Sanggyu | - |
dc.contributor.author | Lee, Doowon | - |
dc.contributor.author | Chae, Soo-Ik | - |
dc.date.accessioned | 2013-01-22T08:24:27Z | - |
dc.date.available | 2013-01-22T08:24:27Z | - |
dc.date.issued | 2009-01 | - |
dc.identifier.citation | IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, Vol.E92A, No.1, pp.279-290 | ko_KR |
dc.identifier.issn | 0916-8508 | - |
dc.identifier.uri | https://hdl.handle.net/10371/80989 | - |
dc.description.abstract | In this paper, we present a high-performance VC-1 main-profile decoder for high-definition (HD) video applications, which can decode HD 720p video streams with 30 fps at 90 MHz. We implemented the decoder with a one-poly eight-metal 0.13 mu m CMOS process, which contains about 261,900 logic gates and on-chip memories of 13.9 KB SRAM and 13.1 KB ROM and occupies an area of about 5.1 mm(2). In designing, the VC-1 decoder, we used a template-based SoC design flow, with which we performed the design space exploration of the decoder by trying various configurations of communication channels. Moreover, we also describe architectures of the computation blocks optimized to satisfy the requirements of VC-1 HID applications. | ko_KR |
dc.description.sponsorship | This work was supported by center for SoC Design Technology (CoSoC), Inter-university Semiconductor Research Center(ISRC) of Seoul Natianal University, and BK21, SystemIC 2010, IP/SoC Center of Seoul, Korea. Chip fabrication was supported by SMIC via KETI/IPCoS. | ko_KR |
dc.language.iso | en | ko_KR |
dc.publisher | Institute of Electronics, Information and Communication Engineers | ko_KR |
dc.subject | SMPTE 421M-2006 VC-1 | ko_KR |
dc.subject | design space exploration | ko_KR |
dc.subject | video decoder | ko_KR |
dc.subject | transaction level modeling | ko_KR |
dc.title | VLSI Implementation of a VC-1 Main Profile Decoder for HD Video Applications | ko_KR |
dc.type | Article | ko_KR |
dc.contributor.AlternativeAuthor | 조진현 | - |
dc.contributor.AlternativeAuthor | 윤상용 | - |
dc.contributor.AlternativeAuthor | 박상규 | - |
dc.contributor.AlternativeAuthor | 이두원 | - |
dc.contributor.AlternativeAuthor | 채수익 | - |
dc.identifier.doi | 10.1587/transfun.E92.A.279 | - |
dc.citation.journaltitle | IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES | - |
dc.description.tc | 0 | - |
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