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Cache Optimization for H.264/AVC Motion Compensation

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dc.contributor.authorYoon, Sangyong-
dc.contributor.authorChae, Soo-Ik-
dc.date.accessioned2013-01-22T08:46:37Z-
dc.date.available2013-01-22T08:46:37Z-
dc.date.issued2008-12-
dc.identifier.citationIEICE TRANSACTIONS ON INFORMATION AND SYSTEMS; Vol.E91D, No.12, pp.2902-2905ko_KR
dc.identifier.issn0916-8532-
dc.identifier.urihttps://hdl.handle.net/10371/80991-
dc.description.abstractIn this letter, we propose a cache organization that substantially reduces the memory bandwidth of motion compensation (MC) in the H.264/AVC decoders. To reduce duplicated memory accesses to P and B pictures, we employ a four-way set-associative cache in which its index bits are composed of horizontal and vertical address bits of the Frame buffer and each line stores in 8 x 2 pixel data in the reference frames. Moreover, we alleviate the data fragmentation problem by selecting its line size that equals the minimum access size of the DDR SDRAM. The bandwidth of the optimized cache averaged over five QCIF IBBP image sequences requires only 129% of the essential bandwidth of an H.264/AVC MC.ko_KR
dc.language.isoenko_KR
dc.publisherIEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENGko_KR
dc.subjectcacheko_KR
dc.subjectDDR SDRAMko_KR
dc.subjectmemory bandwidthko_KR
dc.subjectH.264ko_KR
dc.subjectmotion compensationko_KR
dc.titleCache Optimization for H.264/AVC Motion Compensationko_KR
dc.typeArticleko_KR
dc.contributor.AlternativeAuthor윤상용-
dc.contributor.AlternativeAuthor채수익-
dc.identifier.doi10.1093/ietisy/e91-d.12.2902-
dc.citation.journaltitleIEICE TRANSACTIONS ON INFORMATION AND SYSTEMS-
dc.description.tc2-
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