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Cache Optimization for H.264/AVC Motion Compensation
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Yoon, Sangyong | - |
dc.contributor.author | Chae, Soo-Ik | - |
dc.date.accessioned | 2013-01-22T08:46:37Z | - |
dc.date.available | 2013-01-22T08:46:37Z | - |
dc.date.issued | 2008-12 | - |
dc.identifier.citation | IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS; Vol.E91D, No.12, pp.2902-2905 | ko_KR |
dc.identifier.issn | 0916-8532 | - |
dc.identifier.uri | https://hdl.handle.net/10371/80991 | - |
dc.description.abstract | In this letter, we propose a cache organization that substantially reduces the memory bandwidth of motion compensation (MC) in the H.264/AVC decoders. To reduce duplicated memory accesses to P and B pictures, we employ a four-way set-associative cache in which its index bits are composed of horizontal and vertical address bits of the Frame buffer and each line stores in 8 x 2 pixel data in the reference frames. Moreover, we alleviate the data fragmentation problem by selecting its line size that equals the minimum access size of the DDR SDRAM. The bandwidth of the optimized cache averaged over five QCIF IBBP image sequences requires only 129% of the essential bandwidth of an H.264/AVC MC. | ko_KR |
dc.language.iso | en | ko_KR |
dc.publisher | IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG | ko_KR |
dc.subject | cache | ko_KR |
dc.subject | DDR SDRAM | ko_KR |
dc.subject | memory bandwidth | ko_KR |
dc.subject | H.264 | ko_KR |
dc.subject | motion compensation | ko_KR |
dc.title | Cache Optimization for H.264/AVC Motion Compensation | ko_KR |
dc.type | Article | ko_KR |
dc.contributor.AlternativeAuthor | 윤상용 | - |
dc.contributor.AlternativeAuthor | 채수익 | - |
dc.identifier.doi | 10.1093/ietisy/e91-d.12.2902 | - |
dc.citation.journaltitle | IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS | - |
dc.description.tc | 2 | - |
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