S-Space College of Engineering/Engineering Practice School (공과대학/대학원) Dept. of Electrical and Computer Engineering (전기·정보공학부) Journal Papers (저널논문_전기·정보공학부)
An InGaAs/InP p-i-n-JFET OEIC with a wing-shaped p+-InP layer
- Park, Ki Sung; Oh, Kwang Ryong; Kim, Jeong Soo; Lee, Yong Tag; Kim, Sung June; Kwon, Young Se
- Issue Date
- IEEE Photon. Technol. Lett., vol. 4, pp. 387-389, April 1992
- A new receiver OEIC structure with an InGaAs
p-i-n photodiode, InGaAs self-aligned junction FET’s and a
bias resistor has been fabricated on a semi-insulating InP substrate.
The fabrication processes are highly compatible between
the photodiode and the JFET, and reduction in FET gate length
is achieved using anisotropic selective etching and a two-step
OMVPE growth schedule.
The 80 pm diameter p-i-n detector exhibits a leakage current
of 2 nA and a capacitance of about 0.35 pF at -5 V bias
voltage. Extrinsic transconductance and a gate-source capacitance
of the JFET are typically 45 mS/mm and 4.0 pF/mm at
OV, respectively. The maximum voltage gain of the pre-amplifier
is 12.5 and the bandwidth of the p-i-n amplifier OEIC is expected
to be about 1.2 GHz.
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