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College of Engineering/Engineering Practice School (공과대학/대학원)
Dept. of Electrical and Computer Engineering (전기·정보공학부)
Journal Papers (저널논문_전기·정보공학부)
Fully ion-implanted InP JFET with buried p-layer
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Kim, Sung June | - |
| dc.contributor.author | Jeong, Jichai | - |
| dc.contributor.author | Vella-Coleiro, G. | - |
| dc.contributor.author | Smith, P. | - |
| dc.date.accessioned | 2009-09-08 | - |
| dc.date.available | 2009-09-08 | - |
| dc.date.issued | 1990-01 | - |
| dc.identifier.citation | IEEE Electron Device Lett., vol. 11, pp. 57-58, Jan. 1990 | en |
| dc.identifier.issn | 0741-3106 | - |
| dc.identifier.uri | https://hdl.handle.net/10371/8876 | - |
| dc.description.abstract | A buried p-layer has been successfully implemented in a
fully ion implanted InP JFET for the first time. Using Be co-implanted with Si, a sharp channel profile is obtained. The saturation current has been reduced and the pinch-off characteristic has been improved with a slight decrease in transconductance and cutoff frequency. The equhalent circuits for the JFET with and without the buried p-layer are compared. | en |
| dc.language.iso | en | - |
| dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) | en |
| dc.title | Fully ion-implanted InP JFET with buried p-layer | en |
| dc.type | Article | en |
| dc.contributor.AlternativeAuthor | 김성준 | - |
| dc.contributor.AlternativeAuthor | 정지채 | - |
| dc.identifier.doi | 10.1109/55.46930 | - |
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- College of Engineering/Engineering Practice School (공과대학/대학원)Dept. of Electrical and Computer Engineering (전기·정보공학부)Journal Papers (저널논문_전기·정보공학부)
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