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A low-power high-speed ion-implanted JFET for InP-based monolithic optoelectronic IC's
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Kim, Sung June | - |
| dc.contributor.author | Wang, K. | - |
| dc.contributor.author | Vella-Coleiro, G. | - |
| dc.contributor.author | Lutze, J. | - |
| dc.contributor.author | Ota, Y. | - |
| dc.contributor.author | Guth, G. | - |
| dc.date.accessioned | 2009-09-08 | - |
| dc.date.available | 2009-09-08 | - |
| dc.date.issued | 1987-11 | - |
| dc.identifier.citation | IEEE Electron Device Lett., vol. 8, pp. 518-520, Nov. 1987 | en |
| dc.identifier.issn | 0741-3106 | - |
| dc.identifier.uri | https://hdl.handle.net/10371/8880 | - |
| dc.description.abstract | We describe a high-performance fully ion-implanted planar
InP junction FET fabricated by a shallow (4000-A) n-channel implant, an n+ source-drain implant to reduce FET series resistance, and a p-gate implant to form a shallow (2000-A) abrupt p-n junction, followed by a rapid thermal activation. From FETs with gates 2 pm long, a transconductance of 50 mS/mm and an output impedance of 400 O.mm are measured at zero gate bias with a gate capacitance of 1.2 pF/mm. The FET has a threshold voltage of - 2.4 V, and a saturated drain current of 60 mA/mm at V,, = 0 V with negligible drift. | en |
| dc.description.sponsorship | The authors would like to thank B. C. DeLoach and A. R.
Kmetz for supporting this work, and C. W. Seabury and M. A. Washington for technical discussions | en |
| dc.language.iso | en | - |
| dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) | en |
| dc.title | A low-power high-speed ion-implanted JFET for InP-based monolithic optoelectronic IC's | en |
| dc.type | Article | en |
| dc.contributor.AlternativeAuthor | 김성준 | - |
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