Browse

Transformation and VHDL Code Generation from Coarse-grained Dataflow Graph

Cited 0 time in Web of Science Cited 0 time in Scopus
Authors
Oh, Moonwook; Ha, Soonhoi
Issue Date
1999-01-21
Publisher
한국정보과학회 = Korea Informaion Science Society
Keywords
VHDL Code GenerationDataflow Graph TransformationEDA
Abstract
This paper discusses how we generate VHDL codes for DSP applications described in dataflow graphs. Because the generated VHDL code implements the details of the control structure, we can easily transform it into a running circuit without any modifications, using logic synthesis tools. To improve the quality of the synthesized circuit we apply some graph transformation techniques to the original dataflow graph. We mainly consider coarse-grained dataflow graphs in which each node corresponds to an IP component of considerable size. The proposed facility is very useful for dataflow graph based high level design tools, including our codesign framework PeaCE (Ptolemy extension as Codesign Environment).
Language
English
URI
https://hdl.handle.net/10371/9633
Files in This Item:
Appears in Collections:
College of Engineering/Engineering Practice School (공과대학/대학원)Dept. of Computer Science and Engineering (컴퓨터공학부)Journal Papers (저널논문_컴퓨터공학부)
  • mendeley

Items in S-Space are protected by copyright, with all rights reserved, unless otherwise indicated.

Browse